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PDF ISL12023 Data sheet ( Hoja de datos )

Número de pieza ISL12023
Descripción Low Power RTC
Fabricantes Intersil 
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No Preview Available ! ISL12023 Hoja de datos, Descripción, Manual

Low Power RTC with Battery-Backed SRAM andNOc1NTo-8nOR8taE8Rc-CEItNOCoTMOuErMMRTMESeNIcELhDNonEDriDcEwaDFlwOSRwRuE.ipPnNpLtEeoArWrsCt iCElD.ceMEonSEmtIeNG/rTtNsacSt
DATASHEET
Embedded Temp Compensation ±5ppm with Auto
Daylight Saving
ISL12023
The ISL12023 device is a low power real time clock with an
embedded Temp sensor for oscillator compensation,
clock/calendar, power fail, low battery monitor, brownout
indicator, single periodic or polled alarms, intelligent
battery-backup switching, Battery Reseal™ function and 128
bytes of battery-backed user SRAM.
The oscillator uses an external, low-cost 32.768kHz crystal.
The real time clock tracks time with separate registers for
hours, minutes, and seconds. The device has calendar
registers for date, month, year and day of the week. The
calendar is accurate through 2099, with automatic leap year
correction.
Daylight Savings time adjustment is done automatically, using
parameters entered by the user. Power fail and battery
monitors offer user-selectable trip levels. A time stamp
function records the time and date of switchover from VDD to
VBAT power, and also from VBAT to VDD power.
Applications
• Utility Meters
• POS Equipment
• Medical Devices
• Security Systems
• Vending Machines
• White Goods
• Printers and Copiers
Features
• Real Time Clock/Calendar
- Tracks Time in Hours, Minutes and Seconds
- Day of the Week, Day, Month and Year
• On-chip Oscillator Compensation Over the Operating Temp
Range
- ±5ppm Over -40°C to +85°C
• 10-bit Digital Temperature Sensor Output
- ±2°C Accuracy
• Customer Programmable Day Light Saving Time
• Clock Output with 15 Selectable Frequencies
• 1 Alarm
- Settable to the Second, Minute, Hour, Day of the Week,
Day, or Month
- Single Event or Pulse Interrupt Mode
• Battery Reseal™ Function to Extend Battery Shelf Life
• Automatic Backup to Battery or Super Capacitor
- Operation to VBAT = 1.8V
- 1.0µA Battery Supply Current
• Battery Status Monitor
- 2 User Programmable Levels
• Seven Selectable Voltages for Each Level
• Power Status Brownout Monitor
- Six Selectable Trip Levels, from 2.295V to 4.675V
• Oscillator Failure Detection
• Time Stamp for First VDD to VBAT, and Last VBAT to VDD
• 128 Bytes Battery-Backed User SRAM
• Separate FOUT, IRQ, and LVRST Outputs
• I2C Bus™
- 400kHz Clock Frequency
• 14 Ld TSSOP Package
• Pb-Free (RoHS Compliant)
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
VDD RANGE
(V)
TEMP RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL12023IVZ
12023 IVZ
2.7 to 5.5
-40 to +85
14 Ld TSSOP
M14.173
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020
December 6, 2011
FN6682.3
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2008, 2009, 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. I2C Bus™ is a trademark
owned by NXP Semiconductors Netherlands, B.V. All other trademarks mentioned are the property of their respective owners.

1 page




ISL12023 pdf
ISL12023
I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, TA = -40°C to +85°C, unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 11)
TYP MAX
(Note 7) (Note 11)
UNITS NOTES
tDH Output Data Hold Time
From SCL falling edge crossing
30% of VDD, until SDA enters
the 30% to 70% of VDD window.
0
tR SDA and SCL Rise Time
From 30% to 70% of VDD.
20 + 0.1 x Cb
tF SDA and SCL Fall Time
From 70% to 30% of VDD.
20 + 0.1 x Cb
Cb
Capacitive Loading of SDA or SCL
Total on-chip and off-chip
10
300
300
400
ns
ns 10
ns 10
pF 10
RPU SDA and SCL Bus Pull-up Resistor Off- Maximum is determined by tR
chip and tF.
For Cb = 400pF, max is about
2k~2.5k.
For Cb = 40pF, max is about
15k~20k
1
k10
NOTES:
4. Temperature Conversion is inactive below VBAT = 2.7V. Device operation is not guaranteed at VBAT<1.8V.
5. IRQ/FOUT Inactive.
6. VDD > VBAT +VBATHYS
7. Specified at +25°C.
8. In order to ensure proper timekeeping, the VDD SR- specification must be followed.
9. Limits should be considered typical and are not production tested.
10. These are I2C specific parameters and are not tested, however, they are used to set conditions for testing devices to validate specification.
11. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
12. Specifications are typical and require using a recommended crystal (see “Application Section” on page 24).
13. Minimum VDD and/or VBAT of 1V to sustain the SRAM. The value is based on characterization and it is not tested.
14. To avoid EEPROM recall issues, it is advised to use this minimum power up slew rate. Not tested, shown as typical only.
SDA vs SCL Timing
tF
tHIGH
tLOW
tR
SCL
tSU:STA
SDA
(INPUT TIMING)
SDA
(OUTPUT TIMING)
tSU:DAT
tHD:STA
tHD:DAT
tAA tDH
tSU:STO
tBUF
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ISL12023 arduino
ISL12023
Register Descriptions
The battery-backed registers are accessible following a slave
byte of “1101111x” and reads or writes to addresses [00h:2Fh].
The defined addresses and default values are described in the
Table 1. The battery backed general purpose SRAM has a
different slave address (1010111x), so it is not possible to
read/write that section of memory while accessing the registers.
REGISTER ACCESS
The contents of the registers can be modified by performing a
byte or a page write operation directly to any register address.
The registers are divided into 8 sections. They are:
1. Real Time Clock (7 bytes): Address 00h to 06h.
2. Control and Status (13 bytes): Address 07h to 0Fh and 2Ah to
2Dh.
3. Alarm (6 bytes): Address 10h to 15h.
4. Time Stamp for Battery Status (5 bytes): Address 16h to 1Ah.
5. Time Stamp for VDD Status (5 bytes): Address 1Bh to 1Fh.
6. Daylight Saving Time (8 bytes): 20h to 27h.
7. Temperature (2 bytes): 28h to 29h
8. Crystal Net PPM Correction, NPPM (2 bytes): 2Ah, 2Bh
9. Crystal Turnover Temperature, XT0 (1 byte): 2Ch
10. Crystal ALPHA at high temperature, ALPHA_H (1 byte): 2Dh
11. Scratch Pad (2 bytes): Address 2Eh and 2Fh
Write capability is allowable into the RTC registers (00h to 06h)
only when the WRTC bit (bit 6 of address 08h) is set to “1”. A
multi-byte read or write operation should be limited to one
section per operation for best RTC time keeping performance.
When the previous address is 2Fh, the next address will wrap
around to 00h.
A register can be read by performing a random read at any
address at any time. This returns the contents of that register
location. Additional registers are read by performing a sequential
read. For the RTC and Alarm registers, the read instruction
latches all clock registers into a buffer, so an update of the clock
does not change the time being read. At the end of a read, the
master supplies a stop condition to end the operation and free
the bus. After a read, the address remains at the previous
address +1 so the user can execute a current address read and
continue reading the next register.
It is not necessary to set the WRTC bit prior to writing into the
control and status, alarm, and user SRAM registers.
TABLE 1. REGISTER MEMORY MAP
REG BIT
ADDR. SECTION NAME
7
6
5
4
3
2
1
0 RANGE DEFAULT
00h RTC
SC
0
SC22
SC21
SC20
SC13
SC12
SC11
SC10 0 to 59
00h
01h
MN
0
MN22
MN21
MN20
MN13 MN12 MN11 MN10 0 to 59
00h
02h
HR
MIL
0
HR21
HR20
HR13
HR12
HR11
HR10 0 to 23
00h
03h
DT
0
0
DT21
DT20
DT13
DT12
DT11
DT10 1 to 31
01h
04h
MO
0
0
0
MO20
MO13 MO12 MO11 MO10 1 to 12
01h
05h
YR
YR23
YR22
YR21
YR20
YR13
YR12
YR11
YR10 0 to 99
00h
06h
DW 0 0
0
0
0
DW2
DW1
DW0
0 to 6
00h
07h CSR
SR
BUSY
OSCF DSTADJ
ALM
LVDD LBAT85 LBAT75 RTCF
N/A
01h
08h
INT
ARST WRTC
IM
FOBATB
FO3
FO2
FO1
FO0
N/A
01h
09h
PWR_VDD CLRTS
D
D
D
D VDDTrip2 VDDTrip1 VDDTrip0 N/A
00h
0Ah
PWR_VBAT
RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0 N/A
00h
0Bh
ITRO
IDTR01 IDTR00 IATR05 IATR04 IATR03 IATR02 IATR01 IATR00
N/A
20h
0Ch
ALPHA
D ALPHA6 ALPHA5 ALPHA4 ALPHA3 ALPHA2 ALPHA1 ALPHA0 N/A
46h
0Dh
BETA
TSE
BTSE
BTSR
BETA4 BETA3 BETA2 BETA1 BETA0
N/A
00h
0Eh
FATR
0
0
FFATR5 FATR4 FATR3 FATR2 FATR1 FATR0
N/A
00h
0Fh
FDTR
0
0
0
FDTR4 FDTR3 FDTR2 FDTR1 FDTR0
N/A
00h
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