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PDF CAT24WC256 Data sheet ( Hoja de datos )
| Número de pieza | CAT24WC256 | |
| Descripción | 256K-Bit I2C Serial CMOS E2PROM | |
| Fabricantes | Catalyst Semiconductor | |
| Logotipo |  |
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Preliminary
CAT24WC256
256K-Bit I2C Serial CMOS E2PROM
FEATURES
s 1MHz I2C Bus Compatible*
s 1.8 to 6 Volt Operation
s Low Power CMOS Technology
s 64-Byte Page Write Buffer
s Self-Timed Write Cycle with Auto-Clear
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC256 is a 256K-bit Serial CMOS E2PROM
internally organized as 32,768 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
s Write Protect Feature
– Entire Array Protected When WP at VIH
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-Pin DIP or 8-Pin SOIC
CAT24WC256 features a 64-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
A0
A1
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SOIC Package (K)
A0
A1
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
24WC256 F01
PIN FUNCTIONS
Pin Name
Function
A0, A1
Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6.0V Power Supply
VSS Ground
NC No Connect
SDA
WP
START/STOP
LOGIC
CONTROL
LOGIC
XDEC
SCL
A0
A1
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
512
E2PROM
512 512X512
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
24WC256 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25061-00 6/99 S-1
1 page  
Preliminary
CAT24WC256
I2C BUS PROTOCOL
The features of the I2C bus protocol are defined as
follows:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24WC256 monitors
the SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The bus Master begins a transmission by sending a
START condition. The Master sends the address of the
particular slave device it is requesting. The five most
significant bits of the 8-bit slave address are fixed as
10100(Fig. 5). The CAT24WC256 uses the next two bits
as address bits. The address bits A1 and A0 allow as
many as four devices on the same bus. These bits must
compare to their hardwired input pins. The last bit of the
slave address specifies whether a Read or Write opera-
tion is to be performed. When this bit is set to 1, a Read
operation is selected, and when set to 0, a Write opera-
tion is selected.
After the Master sends a START condition and the slave
address byte, the CAT24WC256 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24WC256 then performs a Read or Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24WC256 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each 8-
bit byte.
When the CAT24WC256 begins a READ mode it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24WC256 will continue to transmit
data. If no acknowledge is sent by the Master, the device
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
ACKNOWLEDGE
5020 FHD F06
1 0 1 0 0 A1 A0 R/W
5
5027 FHD F07
Doc. No. 25061-00 6/99 S-1
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet CAT24WC256.PDF ] | |
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