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PDF THCV236 Data sheet ( Hoja de datos )

Número de pieza THCV236
Descripción SerDes transmitter and receiver
Fabricantes THine Electronics 
Logotipo THine Electronics Logotipo



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THCV231 and THCV236
SerDes transmitter and receiver with bi-directional transceiver
General Description
The THCV231 and THCV236 are designed to
support video data transmission between the host and
display.
THCV231
One high-speed lane can carry up to 14bits data at a
pixel clock frequency from 12MHz to 160MHz.
THCV236
One high-speed lane can carry up to 32bit data and
3bits of synchronizing signals at a pixel clock
frequency from 6MHz to 160MHz by converting
RGB444 to YCbCr422.
The chipset, which has one high-speed data lane,
can transmit video data up to 1080p/60Hz.
The maximum serial data rate is 4.00Gbps/lane.
Block Diagram
Features
Data width selectable
Wide frequency range
AC coupling for high-speed lanes
CDR requires no external frequency reference
Wide range supply voltage from 1.7V to 3.6V
Additional spread spectrum on data stream
2-wire serial interface bridge function(400kbps)
Remote side GPIO control and monitoring
THCV231
QFN32 (5mm x 5mm) with exposed pad ground
THCV236
QFN64 (9mm x 9mm) with exposed pad ground
EU RoHS compliant
D11-D0
HSYNC
VSYNC
CLKIN
THCV231
TXP
TXN
RXP
RXN
THCV236
D31-D0
HSYNC
VSYNC
DE
CLKOUT
Settings
2-wire I/F
SDA/SCL
Controls
OSC
LDO
TCMP
TCMN
RCMP
RCMN
CAPOUT
CAPINA
CAPINP
Controls
OSC
LDO
Settings
2-wire I/F
SDA/SCL
CAPOUT
CAPINA
THCV231_THCV236_Rev.2.30_E
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THCV236 pdf
Pin Description for THCV236
Pin Name
RXP
RXN
HFSEL/RCMP
58
57
61
Pin No.
MAINMODE/ 60
RCMN
HTPDN/
SUBMODE
54
LOCKN/
MSSEL
55
LATEN/SD3/ 11
AIN1/GPIO0
Type
CI
CI
CB/I
CB/I
BO
BO
B
Description
High-Speed CML Signal Input(Main-Link)
High-Speed CML Signal Input(Main-Link)
HFSEL : High Frequency Mode select when PDN1=0.
0 : High Frequency Mode Disable
1 : High Frequency Mode Enable
RCMP : CML Signal Bi-directional Input/Output(Sub-Link) when
PDN1=1.
MAINMODE : Setting V-by-One® HS Mode or Sync Free Mode
when PDN1=0
0 : V-by-One® HS Mode
1 : Sync Free Mode
RCMN : CML Signal Bi-directional Input/Output(Sub-Link)
when PDN1=1.
HTPDN : Hot Plug Detect Output when PDN1=0. Must be
connected to Tx HTPDN with 10kΩ pull-up resistor.
SUBMODE : Sub-Link Mode Select when PDN1=1.
0 : 2-wire serial I/F Mode (default No Clock Stretching mode)
1 : Low Speed Data Bridge Mode
Forbid setting 1 when connecting with THCV231.
LOCKN : Lock Detect Output when PDN1=0. Must be connected
to Tx LOCKN with 10kΩ pull-up resistor.
MSSEL : Sub-Link Master/Slave Select when PDN1=1.
0 : Sub-Link Master side(inside 2-wire serial I/F is slave)
1 : Sub-Link Slave side(inside 2-wire serial I/F is master)
Sub-Link Master is connected to HOST MPU.
Forbid setting 1 when connecting with THCV231.
LATEN : Latch select input under Field BET(Main-Link or
Sub-Link).
0 : NOT Latched result
1 : Latched result
SD3 : Sub-Link Data Input/Output when PDN1=1 and
SUBMODE=1.
When Sub-Link is Master (MSSEL=0), SD3 is output.
When Sub-Link is Slave (MSSEL=1), SD3 is input.
AIN1 : Device ID setting for 2-wire serial I/F when
SUBMODE=0 and MSSEL=0. See Table 18.
GPIO0 : General Purpose Input/Output when SUBMODE=0 and
MSSEL=1.
When GPIO0 is used as Open-Drain Output, it must be connected
with a pull-up resistor to VDD.
When GPIO0 is used as push pull output or input, no external
component is required.
THCV231_THCV236_Rev.2.30_E
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THCV236 arduino
Spread Spectrum Clock Generator (SSCG)
The THCV231 serial data output and the THCV236 parallel data and clock outputs are modulated by
programmable SSCG. The THCV231 and THCV236 SSCG are enabled by only SSEN register. The modulation
rate and modulation frequency variation of output spread is controlled through the SSCG control registers on
each device. Do not enable spread spectrum for both the THCV231 and THCV236 at the same time.
Table 6. SSCG enable signal
Mode Entry Signal
SSEN(register)
Description
0:SSCG Disable
1:SSCG Enable
When customer use the mode and frequency range shown in Table 7, register setting is required according to
Table 8.
Table 7. Main-Link mode and frequency range requiring register setting
MAINMODE
1
1
1
1
*1 Don’t care
*2 See Table 8
Mode Setting
HFSEL
0
0
0
1
COL1
0
0
1
(*1)
COL0
0
1
0
(*1)
Freq.Range[MHz]
(SSCG Enable)
min max
26.6 40
26.6 50
33.3 66.6
50 100
Register
Setting
(*2)
Case1
Case1
Case2
Case3
Step
1
2
3
4
Register Address(HEX)
Sub-Link
Master side
Sub-Link
Slave side
0x70
0xF0
0x76
0xF6
0x78
0xF8
0x7C
0xFC
Table 8. SSCG register setting
Register Value(HEX)
Case1 Case2
Case3
THCV231
THCV236
0x01
0x02
0x02
0x01
0x3C
0x30
0x20
0x35
0x34
0x24
Description
Set 1 to PLL_SET_EN
Set PLL_SET0
Set PLL_SET1
Set PLL_SET2
Modulation frequency fmod can be determined by HFSEL and LFSEL settings, input clock frequency and
FMOD register setting (default value 0xD). Refer to following formula.
f mod
f CLKS S CG
128FMOD
fCLKSSCG is the frequency listed in Table 9 and Table 10.
THCV231_THCV236_Rev.2.30_E
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