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PDF THCV215 Data sheet ( Hoja de datos )

Número de pieza THCV215
Descripción HS High-speed Video Data Transmitter and Receiver
Fabricantes THine Electronics 
Logotipo THine Electronics Logotipo



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No Preview Available ! THCV215 Hoja de datos, Descripción, Manual

THCV215 and THCV216
V-by-One® HS High-speed Video Data Transmitter and Receiver
General Description
THCV215 and THCV216 are designed to support
video data transmission between the host and
display.
The chipset can transmit 39bit video data and 3bit
sync data via only a single differential cable at an
LVDS clock frequency from 20MHz to 100MHz.
The chipset, which has two high-speed data lanes,
can transmit the video data up to 1080p/10b/60Hz,
1080p/12b/60Hz. The maximum serial data rate is
3.75Gbps/lane.
Color
Depth
6bit
8bit
10bit
12bit
Link
Single/Dual
Single/Dual
Single/Dual
Single/Dual
LVDS
Clock Frequency
20MHz to 100MHz
20MHz to 100MHz
20MHz to 85MHz
20MHz to 75MHz
Features
Color depth selectable: 6/8/10/12 bit
Single/Dual Link selectable
AC coupling
LVDS Input internal termination
CORE 1.8V, LVDS 3.3V
Package: 64 pin TSSOP
Wide frequency range
CDR requires no external frequency reference
Supports Spread Spectrum Clocking: Up to
30kHz/0.5%(center spread)
V-by-One® HS standard Version1.4 compliant
Block Diagram
TLA0+/-
TLF0+/-
TLCLK0+/-
TLA1+/-
TLF1+/-
TLCLK1+/-
THCV215
TX0+ RX0+
TX0- RX0-
TX1+ RX1+
TX1- RX1-
THCV216
RLA0+/-
RLF0+/-
RLCLK0+/-
RLA1+/-
RLF1+/-
RLCLK1+/-
Color depth
(6/8/10/12)
Single/Dual
Pre-emphasis
PDN
Controls
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
HTPDN
LOCKN
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Controls
Color depth
(6/8/10/12)
Single/Dual
RS
PDN
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THCV215 pdf
Functional Description
Functional Overview
With V-by-One®HS’s proprietary encoding scheme and CDR (Clock and Data Recovery) architecture, THCV215
and THCV216 enable transmission of 18/24/30/36bits per pixel video data (Rn/Gn/Bn/CONTn), Hsync
(HSYNCn), Vsync (VSYNCn) data and Data Enable (DE) by single/dual differential pair cable with minimal
external components.
THCV215, the transmitter, inputs LVDS data (including video data, Hsync, Vsync and DE) and serializes video
data and Hsync, Vsync data separately, depending on the polarity of DE. DE is a signal which indicates whether
video or Hsync, Vsync data are active. When DE is high, it serializes video data inputs into a single differential
data stream. And it transmits serialized Hsync, Vsync data when DE is low.
THCV216, the receiver, automatically extracts the clock from the incoming data stream and converts the serial
data into video data with DE being high or Hsync, Vsync data with DE being low, recognizing which type of
serial data is being sent by the transmitter. And it outputs the recovered data in the form of LVDS data.
THCV216 can seamlessly operate for a wide range of a serial bit rate from 600Mbps to 3.75Gbps/channel,
detecting the frequency of an incoming data stream, and recovering both the clock and data by itself.
It does not need any external frequency reference, such as a crystal oscillator.
Data Enable Requirement (DE)
There are some requirements for DE as described in Figure 2, Figure 3 and Table 15.
Dual LVDS input to THCV215 should be synchronized in terms of DE transition. See Figure 2.
If DE=Low, Hsync and Vsync data of same cycle are transmitted. Otherwise video data of that are transmitted
(DE=High). SYNC data from receiver in DE=High period are previous data of DE transition. See Figure 3.
The length of DE being low and high is at least 2 clock cycles long as described in Table 15.
Data Enable must be toggled like High -> Low -> High at regular interval.
THCV215
THCV216
Rn/Gn/Bn D[39:0]
CONTn
H
D[39:0]
H
Rn/Gn/Bn
CONTn
HSYNCn
VSYNCn
Hsync
Vsync
DE
L
Hsync
Vsync
L
DE
HSYNCn
VSYNCn
Figure 1. Conceptual diagram of the basic operation of the chipset
Vdiff = (TLCLK0+) (TLCLK0-)
DE DE DE DE DE
Vdiff = (TLC0+) (TLC0-)
Vdiff = (TLCLK1+) (TLCLK1-)
DE DE DE DE DE
Vdiff = (TLC1+) (TLC1-)
Figure 2. Service condition of DE input synchronization
DE
DE
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
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THCV215 arduino
THCV215 Pre-emphasis function (PRE [1:0])
Pre-emphasis can equalize severe signal degradation caused by long distance or high-speed transmission.
Two pins, PRE1 and PRE0, select the strength of pre-emphasis. See Table 4.
PRE[1:0]
L,L
H,L
L,H / H,H
Description
w/o Pre-emphasis
w/ 100% Pre-emphasis
Not available
Table 4. Pre-emphasis function table
THCV215 Power Down function (PDN)
By setting the PDN pin to low, it results in the power down mode. All the internal circuitry turns off and the
both TXn+/- (n=0, 1) outputs turn to VDL.
THCV216 Power Down function (PDN)
By setting the PDN pin to low, it results in the power down mode. All the internal circuitry turns off and the
RLXn+/- (X=A, B, C, D, E, F, CLK, n=0, 1) outputs turn to High-Z.
THCV215 Link Ready function (RDY)
This is a CMOS output for indicating the link status. RDY=High if link is ready.
THCV215-216_Rev.2.70_E
Copyright(C)2016 THine Electronics, Inc.
11/26
THine Electronics, Inc.
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