|
|
PDF ISL97649B Data sheet ( Hoja de datos )
| Número de pieza | ISL97649B | |
| Descripción | TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET | |
| Fabricantes | Intersil | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL97649B (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
|
No Preview Available !
NOc1NTo-8nOR8taE8Rc-CEItNOCoTMOuErMMRTMESeNIcELhDNonEDriDcEwaDFlwOSRwRuE.ipPnNpLtEeoArWrsCt iCElD.ceMEonSEmtIeNG/rTtNsacSt
DATASHEET
TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse
Modulator + RESET
ISL97649B
The ISL97649B is an integrated power management IC (PMIC)
for TFT-LCDs used in notebooks, tablet PCs, and monitors. The
device integrates a boost converter for generating AVDD. VON
and VOFF are generated by a charge pump driven by the
switching node of the boost. The ISL97649B also includes a
VON slice circuit, reset function, and a high performance VCOM
amplifier with DCP (Digitally Controlled Potentiometer) that is
used as a VCOM calibrator.
The AVDD boost converter features a 1.5A /0.18Ω boost FET with
600/1200kHz switching frequency. The gate pulse modulator
can control gate voltage up to 30V, and both the rate and slew
delay time are selectable. The supply monitor generates a
reset signal when the system is powered down.
The ISL97649B provides a programmable VCOM with I2C
interface. One VCOM amplifier is also integrated in the chip. The
output of VCOM is power-up with voltage at the last programmed
8-bit EEPROM setting.
Features
• 2.5V to 5.5V input
• 1.5A, 0.18Ω integrated boost FET
• VON /VOFF supplies generated by charge pumps driven by
boost switch node
• 600/1200kHz selectable switching frequency
• Integrated gate pulse modulator
• Reset signal generated by supply monitor
• Integrated VCOM amplifier
• DCP
- I2C serial interface, address:100111, msb left
- Wiper position stored in 8-bit nonvolatile memory and
recalled on power-up
- Endurance, 1,000 data changes per bit
• UVLO, UVP, OVP, OCP, and OTP protection
• Pb-free (RoHS compliant)
• 28 Ld 4X5 QFN
Applications
• LCD notebook, tablet, and monitor
Pin Configuration
ISL97649B
(28 LD 4X5 QFN)
TOP VIEW
28
FB 1
PGND 2
CE 3
RE 4
VGH 5
VGHM 6
VFLK 7
VDPM 8
27 26 25 24
GND
THERMAL
PAD
23
22 NC
21 CD2
20 NC
19 RESET
18 NC
17 VDIV
16 NEG
15 VOUT
9 10 11 12 13 14
June 27, 2013
FN7927.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011-2013. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL97649B
Electrical Specifications VIN = ENABLE = 3.3V, AVDD = 8V, VON = 24V, VOFF = -6V. Boldface limits apply over the operating
temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 6)
TYP
(Note 7)
MAX
(Note 6)
UNITS
GATE PULSE MODULATOR
VGH
VIH_VDPM
IVGH
VGH Voltage
VDPM Enable Threshold
VGH Input Current
VFLK = 0
RE = 100k, VFLK = VIN
7
1.13
1.215
125
27.5
33
1.30
V
V
µA
µA
VGPM_LO
IGPM_LO
VCEth1
VCEth2
ICE
RVGHM_PD
RONVGH
IDPM
GPM_LO Voltage
VGPM_LO Input Current
CE Threshold Voltage 1
CE Threshold Voltage 2
CE Current
VGHM Pull-down Resistance
VGH to VGHM On Resistance
VDPM Charge Current
2
VGH-2
V
-2 0.1 2 µA
0.6xVIN 0.8xVIN
V
1.215
V
100 µA
1.1 kΩ
23 Ω
10 µA
SUPPLY MONITOR
VIH_VDIV VDIV High Threshold
VIL_VDIV VDIV Low Threshold
VthCD2 CD2 Threshold Voltage
ICD2
CD2 Charge Current
RIL_RESET RESET Pull-down Resistance
tDELAY_RESET RESET Delay on Rising Edge
VDIV rising
VDIV falling
1.265
1.21
1.200
1.280
1.222
1.217
10
650
121.7k*
CD
1.295
1.234
1.234
V
V
V
µA
Ω
s
VCOM AMPLIFIER: RLOAD = 10k, CLOAD = 10pF, UNLESS OTHERWISE STATED
IS_com VCOM Amplifier Supply Current
VOS Offset Voltage
IB Noninverting Input Bias Current
CMIR
Common Mode Input Voltage Range
0.7
1.08
mA
2.5 15 mV
0 nA
0
AVDD
V
CMRR Common-mode Rejection Ratio
60 75
dB
PSRR Power Supply Rejection Ratio
70 85
dB
VOH Output Voltage Swing High
IOUT(source) = 0.1mA
AVDD -
1.39
mV
IOUT(source) = 75mA
AVDD -
1.27
V
VOL Output Voltage Swing Low
ISC Output Short Circuit Current
IOUT(sink) = 0.1mA
IOUT(sink) = 75mA
Pull-up
Pull-down
1.2
1
150 225
150 200
mV
V
mA
mA
SR Slew Rate
25 V/µs
BW Gain Bandwidth
-3dB gain point
20 MHz
5 FN7927.2
June 27, 2013
5 Page 
ISL97649B
voltage. The rectifier diode must meet the output current and
peak inductor current requirements. Table 3 shows some
recommendations for boost converter diode.
TABLE 3. BOOST CONVERTER RECTIFIER DIODE RECOMMENDATIONS
DIODE
PMEG2010ER
VR/IAVG RATING
20V/1A
PACKAGE
SOD123W
MFG
NXP
MSS1P2U
20V/1A
MicroSMP
VISHAY
Output Capacitor
The output capacitor supplies the load directly and reduces the
ripple voltage at the output. Output ripple voltage consists of two
components (Equation 6):
1. Voltage drop due to inductor ripple current flowing through
the ESR of output capacitor.
2. Charging and discharging of output capacitor.
VRIPPLE = ILPK ESR + -V----O---V--–---O--V----I--N-- C-----O-I--O--U----T- -f1-s-
(EQ. 6)
For low ESR ceramic capacitors, the output ripple is dominated
by the charging and discharging of the output capacitor. The
voltage rating of the output capacitor should be greater than the
maximum output voltage.
NOTE: Capacitors have a voltage coefficient that makes their
effective capacitance drop as the voltage across them increases.
COUT in Equation 6 assumes the effective value of the capacitor
at a particular voltage and not the manufacturer’s stated value,
measured at 0V.
Table 4 shows some recommendations for output capacitors.
TABLE 4. BOOST OUTPUT CAPACITOR RECOMMENDATIONS
CAPACITOR
SIZE
MFG
PART NUMBER
10µF/25V
1210
TDK
C3225X7R1E106M
10µF/25V
1210 Murata
GRM32DR61E106K
Compensation
The boost converter of ISL97649B can be compensated by an RC
network connected from the COMP pin to ground. A 15nF and
5.5k RC network is used in the ISL97649BIRTZ-EVALZ evaluation
board. The larger-value resistor and lower-value capacitor can
lower the transient overshoot, but at the expense of loop stability.
Supply Monitor Circuit
The supply monitor circuit monitors the voltage on VDIV and sets
the open-drain output RESET low when VDIV is below 1.28V
(rising) or 1.22V (falling).
There is a delay on the rising edge, controlled by a capacitor on
CD2. When VDIV exceeds 1.28V (rising), CD2 is charged up from
0V to 1.217V by a 10µA current source. When CD2 exceeds
1.217V, RESET goes tri-state. When VDIV falls below 1.22V,
RESET becomes low, with a 650 pull-down resistance. Delay
time is controlled, as shown in Equation 7:
tdelay = 121.7k CD2
(EQ. 7)
For example, delay time is 12.17ms if CD2 = 100nF.
Figure 11 shows the supply monitor circuit timing diagram.
VDIV
CD2
1.217V
1.28V
1.22V
RESET
RESET DELAY TIME IS
CONTROLLED BY CD2
CAPACITOR
FIGURE 11. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM
Gate Pulse Modulator Circuit
The gate pulse modulator circuit functions as a three-way
multiplexer, switching VGHM between ground, GPM_LO, and VGH.
Voltage selection is provided by digital inputs VDPM (enable) and
VFLK (control). High-to-low delay and slew control are provided by
external components on pins CE and RE, respectively.
When VDPM is LOW, the block is disabled, and VGHM is
grounded. When the input voltage exceeds UVLO threshold,
VDPM starts to drive an external capacitor. When VDPM exceeds
1.215V, the GPM circuit is enabled, and the output VGHM is
determined by VFLK, RESET signal, and VGH voltage. If RESET
signal is high and VFLK is high, VGHM is pulled to VGH. When
VFLK goes low, there is a delay controlled by capacitor CE,
following which VGHM is driven to GPM_LO, with a slew rate
controlled by resistor RE. Note that GPM_LO is used only as a
reference voltage for an amplifier, and thus does not have to
source or sink a significant DC current.
Low-to-high transition is determined primarily by the switch
resistance and the external capacitive load. High-to-low transition
is more complex. Consider a case in which the block is already
enabled (VDPM is H). When VFLK is H, if CE is not externally
pulled above threshold voltage 1, Pin CE is pulled low. On the
falling edge of VFLK, a current is passed into Pin CE to charge the
external capacitor up to threshold voltage 2, providing a delay
that is adjustable by varying the capacitor on CE. Once this
threshold is reached, the output starts to be pulled down from
VGH to GPM_LO. The maximum slew current is equal to
500/(RE + 40k), and the dv/dt slew rate is Isl/CLOAD, where
CLOAD is the load capacitance applied to VGHM. The slew rate
reduces as VGHM approaches GPM_LO.
If CE is always pulled up to a voltage above threshold 1, zero
delay mode is selected; thus, there will be no delay from FLK
falling to the point where VGHM starts to fall. Slew down currents
will be identical to the previous case.
At power-down, when VIN falls to UVLO, VGHM is tied to VGH until
the VGH voltage falls to 3V. Once the VGH voltage falls below 3V,
VGHM is not actively driven until VIN is driven. Figure 12 shows
the VGHM voltage based on VIN, VGH, and RESET.
11 FN7927.2
June 27, 2013
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL97649B.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL97649A | TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET | Intersil |
| ISL97649AR5566 | TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET | Intersil |
| ISL97649B | TFT-LCD Supply + DCP + VCOM Amplifier + Gate Pulse Modulator + RESET | Intersil |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |