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PDF ISL6719 Data sheet ( Hoja de datos )
| Número de pieza | ISL6719 | |
| Descripción | 100V Linear Bias Supply | |
| Fabricantes | Intersil | |
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100V Linear Bias Supply
ISL6719
The ISL6719 is a low cost linear regulator for generating a low
voltage bias supply from intermediate distributed voltages
commonly used in telecom and datacom applications. It
provides a single adjustable output rated at 100mA from
either the input source or an auxiliary source such as a
transformer winding. The auxiliary source is selected whenever
it has sufficient voltage to sustain the output.
The ISL6719 may be used as a start-up or a continuous low
power regulator. When operating as a start-up regulator, it is
capable of sourcing 100mA from a 100V source for short
durations. This period of time allows the power supply to
start-up and provide an alternate power source, such as the
output of a transformer winding, to the AUXIN input. This
allows the regulated output to operate from a lower source
voltage to minimize power loss.
Features
• 100V+ input capability
• Adjustable output from 1.5V to 20V
• Up to 100mA output current
• Overcurrent protection
• Over-temperature protection
• ENABLE and ENABLE_N inputs
• Package compliant with IPC2221A, creepage and clearance
spacing requirements
Applications
• Telecom/datacom DC/DC converters
• Low power bias supplies
Pin Configuration
ISL6719
(9 LD DFN)
TOP VIEW
VPWR 1
AUXIN 2
VSW 3
VSW_FB 4
9 GND
8 ENABLE_N
7 ENABLE
6 COMPB
5 COMPA
Ordering Information
PART NUMBER
(Note 1, 2, 3)
PART MARKING
TEMP RANGE
(°C)
PACKAGE
(Pb-free)
PKG.
DWG. #
ISL6719ARZ
19AZ
-40 to +105
9 Ld DFN
L9.3x3
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL6719. For more information on MSL, please see tech brief TB363.
July 15, 2014
FN6555.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2007, 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6719
Electrical Specifications Recommended operating conditions unless otherwise noted. Refer to “Functional Block Diagram” on page 2
and “Typical Application” on page 3. 17V < VPWR < 100V, CVSW = 1µF, IVSW = -3mA, VSW Enabled, TA = -40°C to +105°C (Note 7), Typical values are at
TA = +25°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 8)
TYP
(Note 8)
UNITS
Source Voltage Headroom (VPWR - VSW) VSW = 20V, AUXIN = 0V
Minimum Required Load
IVSW = -100mA
IVSW = -50mA
6.2 V
5.2 V
-3 mA
Maximum VOUT, Faulted VSW_FB
VSW_FB = 0V, VPWR = 100V, AUXIN = 40V
21
25 V
Long Term Stability
TA = +125°C, 1000 hours (Note 8),
VPWR = 48V, VSW = 10V, IVSW = -10mA,
AUXIN = 15V
0.3 %
Operational Current (source)
VPWR = 48V, AUXIN = 17V, VSW = 15V
-100
mA
Current Limit
VPWR = 48V, AUXIN = 15V, VSW = 10V
-100 -230 -400
mA
VSW_FB Bias Current
VPWR = 100V, AUXIN = 40V, VSW = 10V,
VSW_FB = 1.5V
-0.5
1.5 µA
COMPA, COMPB Recommended
Capacitance
(Note 9)
170 220 270
pF
COMPA Voltage
0.7 V
COMPB Voltage
VSW + 5.0
V
ENABLE, ENABLE_N
High Level Input Voltage (VIH)
VPWR = 48V, AUXIN = 0V
2.5 3.0 3.6
V
Low Level Input Voltage (VIL)
VPWR = 48V, AUXIN = 0V
1.6 2.0 2.5
V
Hysteresis
VPWR = 48V, AUXIN = 0V
0.7 1.0 1.3
V
Pull-Up Resistance
Turn-On Delay
Turn-Off Delay
THERMAL PROTECTION
VENABLE = VN_ENABL = 0V
TVSW, 10% - TENABLE, TVSW,10% - TENABLE_N,
IVSW = -3mA
TVSW, 10% - TENABLE, TVSW,10% - TENABLE_N,
IVSW = -50mA
- 100 -
25
40
kΩ
µs
µs
Thermal Shutdown
150 °C
Thermal Shutdown Clear
95 °C
Hysteresis
55 °C
NOTE:
7. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and
are not production tested.
9. Limits established by characterization and are not production tested.
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5
FN6555.2
July 15, 2014
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet ISL6719.PDF ] | |
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