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PDF XR16M670 Data sheet ( Hoja de datos )
| Número de pieza | XR16M670 | |
| Descripción | 1.62V TO 3.63V HIGH PERFORMANCE UART | |
| Fabricantes | Exar | |
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XR16M670
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
DECEMBER 2009
REV. 1.0.1
GENERAL DESCRIPTION
The XR16M6701 (M670) is an enhanced Universal
Asynchronous Receiver and Transmitter (UART) with
32 bytes of transmit and receive FIFOs, selectable
transmit and receive FIFO trigger levels, automatic
hardware and software flow control, and data rates of
up to 16 Mbps at 3.3V, 12.5 Mbps at 2.5V and 7.5
Mbps at 1.8V with 4X data sampling rate.
The Auto RS-485 Half-Duplex Direction control
feature simplifies both the hardware and software for
half-duplex RS-485 applications. In addition, the
Multidrop mode with Auto Address detection
increases the performance by simplifying the
software routines.
The Independent TX/RX Baud Rate Generator
feature allows the transmitter and receiver to operate
at different baud rates. Power consumption of the
M670 can be minimized by enabling the sleep mode
and PowerSave mode.
The M670 has a 16550 compatible register set that
provide users with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M670 is available in 24-pin
QFN, 32-pin QFN and 25-pin BGA packages. All
three packages offer the 16 mode (Intel bus) interface
only.
NOTE: 1 Covered by U.S. Patent #5,649,122.
FEATURES
• Pin-to-pin compatible with XR16L570 in 24-QFN
and 32-QFN packages
• Intel data bus Interface
• 16 Mbps maximum data rate
• Selectable TX/RX FIFO Trigger Levels
• TX/RX FIFO Level Counters
• Independent TX/RX Baud Rate Generator
• Fractional Baud Rate Generator
• Auto RTS/CTS Hardware Flow Control
• Auto XON/XOFF Software Flow Control
• Auto RS-485 Half-Duplex Direction Control
• Multidrop mode w/ Auto Address Detect
• Sleep Mode with Automatic Wake-up
• PowerSave mode in 24-pin QFN package
• Infrared (IrDA 1.0 and 1.1) mode
• 1.62V to 3.63V supply operation
• Crystal oscillator or external clock input
APPLICATIONS
• Personal Digital Assistants (PDA)
• Cellular Phones/Data Devices
• Battery-Operated Devices
• Global Positioning System (GPS)
• Bluetooth
FIGURE 1. XR16M670 BLOCK DIAGRAM
PwrSave
A2:A0
D 7 :D 0
IO R #
IOW #
CS#
IN T
RESET
Intel
Data Bus
Interface
UART
UART
Regs
32 Byte TX FIFO
TX &
IR
RX ENDEC
BRG 32 Byte RX FIFO
Crystal Osc/Buffer
VCC
(1.62 to 3.63 V)
GND
TX, RX,
RTS#, CTS#,
DTR#, DSR#,
RI#, CD#
XTAL1
XTAL2
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
XR16M670
REV. 1.0.1
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
1.0 PRODUCT DESCRIPTION
The XR16M670 (M670) is a high performance single channel UART. The configuration registers set is 16550
UART compatible for control, status and data transfer. Additionally, the M670 channel has 32 bytes of transmit
and receive FIFOs, Automatic RTS/CTS Hardware Flow Control, Automatic Xon/Xoff and Special Character
Software Flow Control, infrared encoder and decoder (IrDA ver 1.0 and 1.1), programmable fractional baud
rate generator with a prescaler of divide by 1 or 4, and data rate up to 16 Mbps. The XR16M670 can operate
from 1.62 to 3.63 volts. The M670 is fabricated with an advanced CMOS process.
Larger FIFO
The M670 provides a solution that supports 32 bytes of transmit and receive FIFO memory, instead of 16 bytes
in the XR16L580. The M670 is designed to work with high performance data communication systems, that
requires fast data processing time. Increased performance is realized in the M670 by the larger transmit and
receive FIFOs, FIFO trigger level control and automatic flow control mechanism. This allows the external
processor to handle more networking tasks within a given time. For example, the XR16L580 with a 16 byte
FIFO, unloads 16 bytes of receive data in 1.53 ms (This example uses a character length of 11 bits, including
start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms
intervals. However with the 32 byte FIFO in the M670, the data buffer will not require unloading/loading for 6.1
ms. This increases the service interval giving the external CPU additional time for other applications and
reducing the overall UART interrupt servicing time. In addition, the selectable FIFO level trigger interrupt and
automatic hardware/software flow control is uniquely provided for maximum data throughput performance
especially when operating in a multi-channel system. The combination of the above greatly reduces the CPU’s
bandwidth requirement, increases performance, and reduces power consumption.
Data Rate
The M670 is capable of operation up to 16 Mbps at 3.3V with 4X internal sampling clock rate. The device can
operate at 3.3V with a 24 MHz crystal on pins XTAL1 and XTAL2, or external clock source of 64 MHz on XTAL1
pin. With a typical crystal of 14.7456 MHz and through a software option, the user can set the prescaler bit and
sampling rate for data rates of up to 3.68 Mbps.
Enhanced Features
The rich feature set of the M670 is available through the internal registers. Automatic hardware/software flow
control, selectable transmit and receive FIFO trigger levels, selectable baud rates, infrared encoder/decoder,
modem interface controls, and a sleep mode are all standard features. MCR bit-5 provides a facility for turning
off (Xon) software flow control with any incoming (RX) character. The M670 includes new features such as 9-bit
(Multidrop) mode, auto RS-485 half-duplex direction control, different baud rate for TX and RX, fast IR mode
and fractional baud rate generator.
5
5 Page 
XR16M670
REV. 1.0.1
1.62V TO 3.63V HIGH PERFORMANCE UART WITH 32-BYTE FIFO
2.7 Programmable Baud Rate Generator with Fractional Divisor
The M670 has independent Baud Rate Generators (BRGs) with prescalers for the transmitter and receiver.
The prescalers are controlled by a software bit in the MCR register. The MCR register bit-7 sets the prescaler
to divide the input crystal or external clock by 1 or 4. The output of the prescaler clocks to the BRG. The BRG
further divides this clock by a programmable divisor between 1 and (216 - 0.0625) in increments of 0.0625 (1/
16) to obtain a 16X or 8X or 4X sampling clock of the serial data rate. The sampling clock is used by the
transmitter for data bit shifting and receiver for data sampling. For transmitter and receiver, the M670 provides
respective BRG divisors. The BRG divisor (DLL, DLM, and DLD registers) defaults to the value of ’1’ (DLL =
0x01, DLM = 0x00 and DLD = 0x00) upon reset. Therefore, the BRG must be programmed during initialization
to the operating data rate. The DLL and DLM registers provide the integer part of the divisor and the DLD
registers provides the fractional part of the divisor. The four lower bits of the DLD are used to select a value
from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). Programming the Baud Rate Generator
Registers DLL, DLM and DLD provides the capability for selecting the operating data rate. Table 3 shows the
standard data rates available with a 24MHz crystal or external clock at 16X clock rate. If the pre-scaler is used
(MCR bit-7 = 1), the output data rate will be 4 times less than that shown in Table 3. At 8X sampling rate, these
data rates would double. And at 4X sampling rate, they would quadruple. Also, when using 8X sampling mode,
please note that the bit-time will have a jitter (+/- 1/16) whenever the DLD is non-zero and is an odd number.
When using a non-standard data rate crystal or external clock, the divisor value can be calculated with the
following equation(s):
Required Divisor (decimal)=(XTAL1 clock frequency / prescaler) /(serial data rate x 16), with 16X mode, DLD[5:4]=’00’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 8), with 8X mode, DLD[5:4] = ’01’
Required Divisor (decimal)= (XTAL1 clock frequency / prescaler / (serial data rate x 4), with 4X mode, DLD[5:4] = ’10’
The closest divisor that is obtainable in the M670 can be calculated using the following formula:
ROUND( (Required Divisor - TRUNC(Required Divisor) )*16)/16 + TRUNC(Required Divisor), where
DLM = TRUNC(Required Divisor) >> 8
DLL = TRUNC(Required Divisor) & 0xFF
DLD = ROUND( (Required Divisor-TRUNC(Required Divisor) )*16)
In the formulas above, please note that:
TRUNC (N) = Integer Part of N. For example, TRUNC (5.6) = 5.
ROUND (N) = N rounded towards the closest integer. For example, ROUND (7.3) = 7 and ROUND (9.9) = 10.
A >> B indicates right shifting the value ’A’ by ’B’ number of bits. For example, 0x78A3 >> 8 = 0x0078.
2.7.1 Independent TX/RX BRG
The XR16M670 has two independent sets of TX and RX baud rate generator. Please see the Figure 7. TX and
RX can work in different baud rate by setting DLD, DLL and DLM register. For example, TX can transmit data
to the remote UART at 9600 bps while RX receives data from remote UART at 921.6 Kbps. For the baud rate
setting, please See ”Section 4.13, Baud Rate Generator Registers (DLL, DLM and DLD) - Read/Write” on
page 36..
11
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| PDF Descargar | [ Datasheet XR16M670.PDF ] | |
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