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PDF XR16C854D Data sheet ( Hoja de datos )

Número de pieza XR16C854D
Descripción 2.97V TO 5.5V QUAD UART
Fabricantes Exar 
Logotipo Exar Logotipo



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XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
APRIL 2013
REV. 3.1.0
GENERAL DESCRIPTION
The XR16C854/854D1 (854) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 128 bytes of transmit and receive
FIFOs, transmit and receive FIFO counters and
trigger levels, automatic hardware and software flow
control, and data rates of up to 2 Mbps.
Each UART has a set of registers that provide the
user with operating status and control, receiver error
indications, and modem serial interface controls.
System interrupts may be tailored to meet design
requirements. An internal loopback capability allows
onboard diagnostics.
The 854 is available in 64-pin LQFP, 68-pin PLCC
and 100-pin QFP packages. The 64-pin package
only offers the 16 mode interface, but the 68 and 100
pin packages offer an additional 68 mode interface
which allows easy integration with Motorola
processors.
The XR16C854CV (64 pin) offers three state interrupt
outputs while the XR16C854DV provides continuous
interrupt outputs. The 100 pin package provides
additional FIFO status outputs (TXRDY# and
RXRDY# A-D), separate infrared transmit data
outputs (IRTX A-D) and channel C external clock
input (CHCCLK). The XR16C854/854D is compatible
with the industry standard ST16C554/554D and
ST16C654/654D.
NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787.
FEATURES
Added feature in devices with top mark date code of
"F2 YYWW" and newer:
s 5 volt tolerant inputs
2.97 to 5.5 Volt Operation
Pin-to-pin compatible with the industry standard
ST16C554 and ST16C654 and TI’s TL16C554N
and TL16C754BFN
Intel or Motorola Data Bus Interface select
Four independent UART channels
s Register Set Compatible to 16C550
s Data rates of up to 2 Mbps
s Transmit and Receive FIFOs of 128 bytes
s Programmable TX and RX FIFO Trigger Levels
s Transmit and Receive FIFO Level Counters
s Automatic Hardware (RTS/CTS) Flow Control
s Selectable Auto RTS Flow Control Hysteresis
s Automatic Software (Xon/Xoff) Flow Control
s Wireless Infrared (IrDA 1.0) Encoder/Decoder
Sleep Mode (200 uA typical)
Crystal oscillator or external clock input
APPLICATIONS
Portable Appliances
Telecommunication Network Routers
Ethernet Network Routers
Cellular Data Devices
Factory Automation and Process Control
FIGURE 1. XR16C854 BLOCK DIAGRAM
A2:A0
D7:D0
IOR#
IO W #
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
Data Bus
Interface
UART Channel A
UART
Regs
BRG
128 Byte TX FIFO
TX & RX
IR
ENDEC
128 Byte RX FIFO
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
2.97V to 5.5V VCC
GND
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#, OP2A#
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#, OP2B#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#, OP2C#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#, OP2D#
XTAL1
XTAL2
854 BLK
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com

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XR16C854D pdf
REV. 3.1.0
Pin Description
XR16C854/854D
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
NAME
64-LQFP
PIN #
68-PLCC
PIN#
100-QFP
PIN #
TYPE
DESCRIPTION
IOR# 40 52 66 I When 16/68# pin is at logic 1, the Intel bus interface is selected
(N.C.)
and this input becomes read strobe (active low). The falling edge
instigates an internal read cycle and retrieves the data byte from
an internal register pointed by the address lines [A2:A0], puts the
data byte on the data bus to allow the host processor to read it on
the rising edge.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input is not used.
IOW#
(R/W#)
9
18 15 I When 16/68# pin is at logic 1, it selects Intel bus interface and this
input becomes write strobe (active low). The falling edge instigates
the internal write cycle and the rising edge transfers the data byte
on the data bus to an internal register pointed by the address lines.
When 16/68# pin is at logic 0, the Motorola bus interface is
selected and this input becomes read (logic 1) and write (logic 0)
signal. Motorola bus interface is not available on the 64 pin pack-
age.
CSA#
(CS#)
7
16 13 I When 16/68# pin is at logic 1, this input is chip select A (active low)
to enable channel A in the device.
When 16/68# pin is at logic 0, this input becomes the chip select
(active low) for the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSB#
11
20
17 I When 16/68# pin is at logic 1, this input is chip select B (active low)
(A3) to enable channel B in the device.
When 16/68# pin is at logic 0, this input becomes address line A3
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSC#
38
50
64 I When 16/68# pin is at logic 1, this input is chip select C (active low)
(A4) to enable channel C in the device.
When 16/68# pin is at logic 0, this input becomes address line A4
which is used for channel selection in the Motorola bus interface.
Motorola bus interface is not available on the 64 pin package.
CSD#
42
54
68 I When 16/68# pin is at logic 1, this input is chip select D (active low)
(N.C.)
to enable channel D in the device.
When 16/68# pin is at logic 0, this input is not used.
Motorola bus interface is not available on the 64 pin package.
INTA
(IRQ#)
6
15 12 O When 16/68# pin is at logic 1 for Intel bus interface, this ouput
(OD) becomes channel A interrupt output. The output state is defined by
the user and through the software setting of MCR[3]. INTA is set to
the active mode when MCR[3] is set to a logic 1. INTA is set to the
three state mode when MCR[3] is set to a logic 0 (default). See
MCR[3].
When 16/68# pin is at logic 0 for Motorola bus interface, this output
becomes device interrupt output (active low, open drain). An exter-
nal pull-up resistor is required for proper operation.
Motorola bus interface is not available on the 64 pin package.
5

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XR16C854D arduino
XR16C854/854D
REV. 3.1.0
2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO
2.2 5-Volt Tolerant Inputs
For devices that have top mark date code "F2 YYWW" and newer, the 854 can accept a voltage of up to 5.5V
on any of its inputs (except XTAL1) when operating from 2.97V to 5.5V. XTAL1 is not 5 volt tolerant. Devices
that have top mark date code "DC YYWW" and older do not have 5V tolerant inputs.
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs in all four channels to their
default state (see Table 19). An active high pulse of longer than 40 ns duration will be required to activate the
reset function in the device. Following a power-on reset or an external reset, the 854 is software compatible
with previous generation of UARTs, 16C454 and 16C554 and 16C654.
2.4 Device Identification and Revision
The XR16C854 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x14 for the
XR16C854 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
2.5 Channel Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. During Intel Bus Mode (16/68# pin is connected to VCC), a
logic 0 on chip select pins, CSA#, CSB#, CSC# or CSD# allows the user to select UART channel A, B, C or D
to configure, send transmit data and/or unload receive data to/from the UART. Selecting all four UARTs can be
useful during power up initialization to write to the same internal registers, but do not attempt to read from all
four uarts simultaneously. Individual channel select functions are shown in Table 1 below.
TABLE 1: CHANNEL A-D SELECT IN 16 MODE
CSA# CSB# CSC# CSD#
FUNCTION
1111
UART de-selected
0111
Channel A selected
1011
Channel B selected
1101
Channel C selected
1110
Channel D selected
0000
Channels A-D selected
During Motorola Bus Mode (16/68# pin is connected to GND), the package interface pins are configured for
connection with Motorola, and other popular microprocessor bus types. In this mode the 854 decodes two
additional addresses, A3 and A4, to select one of the four UART ports. The A3 and A4 address decode
function is used only when in the Motorola Bus Mode. See Table 2 below.
TABLE 2: CHANNEL A-D SELECT IN 68 MODE
CS# A4 A3
FUNCTION
1 N/A N/A
UART de-selected
000
Channel A selected
001
Channel B selected
010
Channel C selected
011
Channel D selected
11

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