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PDF XRT81L27 Data sheet ( Hoja de datos )
| Número de pieza | XRT81L27 | |
| Descripción | SEVEN CHANNEL E1 LINE INTERFACE UNIT | |
| Fabricantes | Exar | |
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XRT81L27
NOVEMBER 2001
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
GENERAL DESCRIPTION
The XRT81L27 is an optimized seven-channel, ana-
log, 3.3V, line interface unit, fabricated using low pow-
er CMOS technology. The device contains seven in-
dependent E1 channels, including data and clock re-
covery circuits. It is primarily targeted towards the
SDH multiplexers that accommodate TU12 Tributary
Unit Frames. Line cards in these units multiplex 21 E1
channels into higher SDH rates. Devices with seven
E1 interfaces such as the XRT81L27 provide the
most efficient method of implementing 21-channel
line cards. Each channel performs the driver and re-
ceiver functions necessary to convert bipolar signals
to logical levels and vice versa.
The receiver input accepts transformer or capacitor
coupled signals, while the transmitter is coupled to
the line using a 1:2 step-up transformer. The same
transformer configuration can be used for both bal-
anced 120 Ω and unbalanced 75 Ω interfaces. The
Receiver Loss of Original Detection is compliant to
G.775 and in Host Mode, the number of zeros re-
ceived before RLOS is declared can be increased to
4096 bits. This feature provides the user with the flex-
ibility to implement RLOS specifications that require
greater than G.775 requirements
FEATURES
• Seven (7) Independent E1 (CEPT) Line Interface
Units (Transmitter, Receiver, and Recovery)
• Transmit Output Pulses that are Compliant with the
ITU-T G.703 Pulse Template Requirement for
2.048Mbps (E1) Rates
• On-Chip Pulse Shaping for both 75Ω and 120Ω line
drivers
• Receiver Can Either Be Transformer or Capacitive-
Coupled to the Line
• Detects and Clears LOS (Loss of Signal) Per ITU-T
G.775 and ETS 300 233 (programmable from Host)
• Compliant with the ITU-T G.823 Jitter Tolerance
Requirements
• 3.3V operation with 5V Input compatibility
• Low power consumption
APPLICATIONS
• SDH and lPDH Multiplexers
• E1 Digital Cross-Connect Systems
• DECT (Digital European Cordless Telephone) Base
Stations
• CSU/DSU Equipment
FIGURE 1. BLOCK DIAGRAM
SDO
SDI
SClk
CS
RST
Microprocessor
Serial
Interface
(MSI)
LBM
LBEN
SR/DR
MODE
RClkP
ICT
Global
Control
MCLK
TClkP
TPOS_n
TCLK_n
TNEG_n
PDTx_n
MCLK
TCLKP
Encoded
PDATA
Encoder
Encoded
NDATA
Timing
Control
MUX
TAOS_n
LOS_n
LOS
Detect
Remote
Loopback
Channel 6
Channel 5
Channel 4
Channel 3
Channel 2
Channel 1
Channel 0
Timing
Control
TX
Pulse
Shaper
Line
Driver
TTIP_n
TRING_n
Digital
Loopback
Analog
Loopback
RPOS_n
RClk_n
RNEG_n
Decoder
Data & Timing
Recovery
MUX
Peak
Detector
Receive
Equalizer
RTIP_n
RRING_n
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
PIN DESCRIPTIONS
NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.
PIN #
NAME
TYPE
DESCRIPTION
1 RClk_0
2 LOS_0
3 RST
LBEN
4 RTIP_0
5 RRING_0
6 PDTx_0
7 TTIP_0
8 TVDD_0
9 TRING_0
10 TGND_0
11 PDTx_2
12 TTIP_2
13 TVDD_2
14 TRING_2
15 TGND_2
16 AVDD
17 RTIP_2
18 RRING_2
19 AGND
20 RTIP_4
21 RRING_4
22 PDTx_4
23 TTIP_4
24 TVDD_4
25 TRING_4
O
O
I-H
I
I
I-H
O
Vdd
O
Gnd
I-H
O
Vdd
O
Gnd
AVdd
I
I
Gnd
I
I
I-H
O
Vdd
O
Receiver 0 Clock Output
Receiver 0 Loss of Signal:
This signal is asserted "High" to indicate loss of signal at the receive
input.
Reset (Active-low): (Host Mode)
“Low” Resets the register contents to zero.
Loop-back Enable (Active-low): (Hardware Mode)
“Low” for Loop-back mode enable.
Receiver 0 Bipolar Positive Input:
Receiver 0 Bipolar Negative Input:
Power-down Transmitter 0:
This pin is operational for both Host or Hardware Mode.
This pin MUST be pulled “Low” to enable TTIP_0 and TRING_0 output
buffers.
Pull this pin "High" to power-down channel 0 transmitter and set TTIP_0
and TRING_0 outputs to high impedance.
Transmitter 0 Tip Output: Positive bipolar data output to the line
Transmitter 0 Positive Supply (3.3V± 5%)
Transmitter 0 Ring Output: Negative bipolar data output to the line.
Transmitter 0 Supply Ground
Power-down Transmitter 2: (see pin 6)
Transmitter 2 Tip Output: Positive bipolar data output to the line.
Transmitter 2 Positive Supply(3.3V± 5%)
Transmitter 2 Ring Output: Negative bipolar data output to the line.
Transmitter 2 Supply Ground.
Analog Positive Supply(3.3V± 5%)
Receiver 2 Bipolar Positive Input:
Receiver 2 Bipolar Negative Input:
Analog Supply Ground.
Receiver 4 Bipolar Positive Input:
Receiver 4 Bipolar Negative Input:
Power-down Transmitter 4: (see pin 6)
Transmitter 4 Tip Output: Positive bipolar data output to the line.
Transmitter 4 Positive Supply(3.3V± 5%)
Transmitter 4 Ring Output: Negative bipolar data output to the line.
3
5 Page 
áç
XRT81L27
SEVEN CHANNEL E1 LINE INTERFACE UNIT WITH CLOCK RECOVERY
REV. 1.1.0
PIN DESCRIPTIONS
NOTE: I -H indicates an input pin with a 50kΩ pull-up Resistor, I-L indicates an input pin with a 50kΩ pull-down resistor.
PIN #
127
128
NAME
RPOS_0/
RDATA_0
RNEG_0/
LCV_0
TYPE
O
O
DESCRIPTION
Receiver 0 Positive /NRZ Data Output: (see pin 35)
Receiver 0 Negative Data Output: (see pin 34)
TABLE 1: PIN NUMBER BY PIN NAME
CHANNEL RTIP RRING TTIP TRING RCLK RPOS RNEG LOS
0
45
7
9
1 127 128 2
1 93 92 90 88 96 98 97 95
2 17 18 12 14 125 123 124 126
3 80 79 85 83 100 102 101 99
4 20 21 23 25 33 35 34 36
5 77 76 74 72 60 58 59 57
6 68 67 28 30 64 62 63 61
GLOBAL SIGNALS
RST
3
RClkP 65
MODE 32
MClk 70
SR/DR 69
TClkP 66
ICT 94
CONTROLLER INTERFACE
SDO 47
SDI 48
SClk
POWER PINS
VDD 41 56 122
GND 42 55 121
AVDD 16 81 103
AGND 19 78 104
TCLK TPOS TNEG PDT TAOS TVDD TGND
120 119 118 6 117 8 10
105 106 107 91 108 89 87
116 115 114 11 113 13 15
109 110 111 86 112 84 82
37 38 39 22 40 24 26
54 53 52 75 51 73 71
43 44 45 27 46 29 31
49 CS 50
9
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| PDF Descargar | [ Datasheet XRT81L27.PDF ] | |
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