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PDF XRD9836 Data sheet ( Hoja de datos )
| Número de pieza | XRD9836 | |
| Descripción | 16-BIT PIXEL GAIN AFE | |
| Fabricantes | Exar | |
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XRD9836
JUNE 2003
16-BIT PIXEL GAIN AFE
REV. 1.0.0
GENERAL DESCRIPTION
The XRD9836 is a precision 16-bit analog front-end
(AFE) for use in 3-channel/1-channel CCD/CIS docu-
ment imaging applications. Pixel-by-pixel gain and
offset for each of the 3 channels are controlled using
a time multiplexed parallel input. Offset and Gain are
sequentially supplied for red, green, and blue. The
outputs from each of the three channels are transmit-
ted time multiplexed with the high order byte first fol-
lowed by the low order byte for red, blue and green.
FEATURES
• 16-bit resolution ADC, 30MHz Sampling Rate
• 10-bit accurate linear programmable gain range select-
able as either 2-to-20 V/V or 1-to-10 V/V per channel
• Fully-differential input pins and internal path
• Sampling rates from 1.0 MSPS to 10.0 MSPS per chan-
nel for 3 -Channel mode and up to 15.0 MSPS in single
channel mode.
• Pixel-by-Pixel Offset and Gain control through a parallel
interface running at a maximum 60 Mbyte/sec. data rate
• A microprocessor serial port to control various modes of
operation
• Fixed Gain/Offset Mode (FGOM) or Pixel by Pixel Gain/
Offset Mode (PPGOM)
• Alternate Pixel Offset Adjust Mode (APOAM)
• Low Power CMOS=280mW (typ. @ 3V); Power-Down
Mode=1mW (typ. @ 3V with static clocks)
• Single Power Supply (3.0 to 3.6 Volts) with Max CCD
input signal of 1V and reset pulse up to 0.5V
• High ESD Protection: 2000 Volts Minimum
APPLICATIONS
• Scanners, MFP’s
FIGURE 1. BLOCK DIAGRAM
OFFSET/GAIN
INPUT 10
ADCLK
IE
GRN+
RED-
RED+
GRN-
BLUE+
BLUE-
CAPP
CAPN
CMREF
REXT
ANALOG INPUTS
BIAS
RED GAIN
REGISTER
RED OFFSET
REGISTER
Red Gain
10
10
Red Offset
RED
CDS &
PGA
GREEN GAIN Green Gain
REGISTER
10
GREEN OFFSET 10
REGISTER Green Offset
Green
CDS &
PGA
BLUE GAIN
REGISTER
BLUE OFFSET
REGISTER
Blue Gain
10
10
Blue Offset
BLUE
CDS &
PGA
XRD9836
M
U
D
16-BIT 16
E
M
X
30MHz
ADC
U
X
RED HIGH ORDER
ADC OUT
RED LOW ORDER
ADC OUT
GREEN HIGH ORDER
ADC OUT
GREEN LOW ORDER
ADC OUT
BLUE HIGH ORDER
ADC OUT
BLUE LOW ORDER
ADC OUT
SERIAL PORT
SCLK
SDATA
LOAD
TIMING
VSAMP
BSAMP
LCLMP
POWER
33
Avdd
Agnd
Dvdd
22
Ognd
Ovdd
Dgnd
8 ADC
OUT
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
ELECTRICAL CHARACTERISTICS - XRD9836 (con’t)
Unless otherwise specified: AVDD=DVDD=3.3V, ADCLK = 30 MHz, REXT=10KΩ, Ta=25C
PARAMETER
SYMBOL
Input Voltage
Range
INVSR
MIN.
Input Leakage
Current
Input Switch On
Resistance
Iin
Ron
-40
Input Switch
Off Resistance
Roff
Internal Voltage
Clamp CDS
Input
(inverting)
Vclampccd
Internal Voltage
Clamp S/H Input
(Non-inverting)
Vclampsh
100
1.1
-0.2
TYP.
CDS - S/H
MAX.
1.0
0.5
1.2
8 40
50 150
1.25 1.4
UNIT
CONDITIONS
V CCD Mode,
Gain = 1 to 10
V CCD Mode,
Gain = 2 to 20
V CIS Mode,
Gain = 0.5 to 5
nA
Ω
MEGΩ
At input pins: RED+/-,
GRN+/-, BLU+/- when
BSAMP is active
guaranteed by design
At input pins: RED+/-,
GRN+/-, BLU+/- when
BSAMP is inactive
guaranteed by design
V CCD MODE
0.0 0.2
V
CIS MODE
PARAMETER
SYMBOL
Fine Offset
Range
Fine Offset
Step
Dynamic
Offset Range
Dynamic
Offset Step
FOFR-
FOFR+
FOFRES
DOFR-
DOFR+
DOFRES
MIN TYP MAX
OFFSET SPECIFICATIONS
-200
80
-128
+127
-80
200
0.25
-125
120
-80
+160
0.25
-55
250
UNIT
mV
mV
mV
mV
mV
mV
CONDITIONS
10bit
10bit
5
5 Page 
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XRD9836
16-BIT PIXEL GAIN AFE
REV. 1.0.0
GAIN SELECT:
The XRD9836’s Gain range is selectable to either 1 to
10 or 2 to 20 with the Gain Select Bit. If Gain of 1 to
10 is selected (Gain Select bit = 0), the maximum in-
put is 1.0V. If Gain of 2 to 20 is selected (Gain Select
bit = 1), the maximum input is 0.5V.
PARALLEL PORT FOR PIXEL OFFSET
AND GAIN CONTROL (OGI):
The timing diagram in Figure 4 shows the Offset and
Gain Inputs (OGI) and ADCLK in relationship to
VSAMP.
IE
VSAMP
3 - Channel OGI Timing
Tev
Tva
ADCLK
OGI 10-bit
parallel input
RG RO GG GO BG BO
Togis
Togih
RG
IE
VSAMP
ADCLK
OGI 10-bit
parallel input
1 - Channel OGI Timing
Tev
Tva
Gain
Togis
Offset
Gain
Togih
FIGURE 4. OGI TIMING (ADCLKPOL=0, VSAMPPOL=0)
The ASIC chip will be clocking OGI data at six times
the pixel rate clock in 3-CH mode and two times the
pixel rate in 1-CH mode. The gain data is grabbed on
the rising edge of ADCLK and the offset data on the
falling edge of ADCLK. The OGI port is read into in-
ternal pixel gain and offset registers only when Input
Enable (IE) is active before the sampling edge of
VSAMP as shown above. As noted the RGB gain/off-
set data is synchronized to sampling edge of VSAMP.
Note that ADCLK frequency is 3X the pixel rate in 3-
CH mode and 1X the pixel rate in 1-CH mode. The
ADCLK’s duty cycle is required to be 50%. It is as-
sumed that the OGI port and ADCLK input have
matched output drivers inside the ASIC, matched
trace lengths on the PCB between the ASIC and the
XRD9836, and matched delays at input buffers inside
the XRD9836 in order to receive OGI data on both
edges of ADCLK error free.
The latency between the input of the parallel inputs
and their effective application is 1 pixel. The user is
also reminded that data coming out of the ADC out-
puts will have latency from the gain and offset provid-
ed (10 ADC cycles for single color and 12 cycles for
3-color). This latency includes the cycles to put the
gain and offset data into the registers and the latency
of the ADC itself (9 ADCLK cycles).
Sampling of the OGI parallel input port is defined as
the red gain data being the first pulse of ADCLK after
VSAMP, therefor VSAMP must occur before a rising
edge of ADCLK. It is also recommended that
VSAMP__OGI_DLY (DelayD[7:4]) should be smaller
than OGI_DLY (DelayA[7:4]) to make sure the correct
data is sampled, and that relationship is not reversed
internally.
PARALLEL PORT FOR ADC OUTPUT
(ADCDO):
The timing diagram, Figure 5, shows the ADC output
(ADCDO). The XRD9836 will be clocking ADC high
order bytes on the rising edge of ADCLK and clocking
ADC low order bytes on the falling edge of ADCLK.
As noted the RGB data is synchronized to sampling
edge of VSAMP.
3 - Channel ADCDO Timing
VSAMP
ADCLK
ADCDO 8-bit
parallel output
BDL RDH RDL GDH GDL BDH BDL
Tadcdo
VSAMP
ADCLK
ADCDO 8-bit
parallel output
1 - Channel ADCDO Timing
DH
Tadcdo
DL
FIGURE 5. ADCDO TIMING (ADCLKPOL=0, VSAMPPOL=0)
PIXEL GAIN/OFFSET CONTROL (FGOM
OR PGOM):
Figure 6 shows the block diagram of the CDS/PGA/
Offset DACs/ADC signal path. The offset for each
channel is controlled by a 10-bit Dynamic offset DAC
before the CDS amplifier and a 10-bit Fine offset DAC
after the PGA amplifier. Thus, the total offset of each
channel is controlled by two 10-bit offset DACs. The
Dynamic offset DAC will have a range of -80mV to
+160mV, with the ability to adjust the CDS stage off-
set to within +/- 0.25mV. The Fine offset DAC will
11
11 Page | ||
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| PDF Descargar | [ Datasheet XRD9836.PDF ] | |
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