|
|
PDF XRT85L61 Data sheet ( Hoja de datos )
| Número de pieza | XRT85L61 | |
| Descripción | BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR | |
| Fabricantes | Exar | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de XRT85L61 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
|
No Preview Available !
xr
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
OCTOBER 2004
GENERAL DESCRIPTION
The XRT85L61 is an integrated E1, T1, 64KHz
Centralized Clock interface for T1 (1.544Mbps) 100Ω,
E1 (2.048Mbps) 75Ω or 120Ω applications.
The XRT85L61 extracts either 2048kHz or 1544 kHz
clock signals from an E1 (2.048 MHz), T1 (1.544
Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz
clock signals from the 64kHz reference clock input.
The XRT85L61 includes an on-chip crystal-less jitter
attenuator with 32 bit FIFO that can either be enabled
or disabled.
FEATURES
• Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
• Extracts 2048 kHz, 1544 kHz clock and data
components
• Extracts 64 KHz and 8 kHz, 400 Hz clock
information
• Line Code Violation alarms
REV. 1.0.2
• On-chip digital clock recovery circuit
• Supports 75Ω and 120Ω (E1), 100Ω (T1)
applications.
• Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
• Receive loss of signal (RLOS) output
• Meets Telcordia GR-1244-CORE Section 3.4.1 R3-
27 specification
• Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
• Single +3.3V Supply Operation
• Logic inputs accept either 3.3 V or 5 V levels
• 28 pin TSSOP package
APPLICATIONS
• Universal Clock Synchronization for G.703 Telecom
Formats
• T1/E1 Line Receiver with Clock and Data Recovery
• DSLAM
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
RCLKINV
DATA_INV
DATAMUT
JAEN
Reference Inputs
MCLK1
(1.544 MHz for T1)
MCLK2
(2.048 MHz for E1
or 64 kbps)
Line Side
(T1 or E1 or 64 kbps input)
RTIP
RRING
S1
S2
S3
Master Clock
Generator
Rx
Equalizer
Peak Detector
and Slicer
Mode Select
T1, E1 or 64 kbps
Clock and
Data
Recovery
Jitter
Attenuator
LOS
Detector
Clock
Extractor
Line code
and clock
violation
Detector
RPOS
RNEG
RCLK
(64kHz,1544kHz or 2048kHz)
8 kHz (for 64 kbps)
400 Hz (for 64 kbps)
RCLK_LCV/AIS
8 kHz_LCV/BPV
400 Hz_LCV
RLOS
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
xr
REV. 1.0.2
PIN DESCRIPTIONS
PIN #
12
13
14
15
SYMBOL
S2
S3
NC
DATMUT
16 RNEG
17 RPOS
18 RCLK
19 DGND
20 DVDD
21 RLOS
22 400Hz
23 8 kHz
24 400Hz_LCV
25 8 kHz_LCV/
BPV
26 RCLK_LCV/AIS
27 DATA_INV
28 RCLK_INV
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
TYPE
I
I
***
I
O
O
O
***
***
O
O
O
O
O
O
I
I
DESCRIPTION
Mode Select
Mode Select
This pin must be grounded for normal operation
Data Muting:
Connect this pin “High” to mute data output to “Low” state at RPOS/
RNEG. The RLOS pin can be connected to this pin to mute the output
when RLOS occurs.
NOTE: Internally Pulled down with 50 kΩ resistor
Receive Negative Data Output:
The data is half clock cycle wide.
Receive Positive Data Output:
The data is half clock cycle wide
Receive Clock Output
Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock
Digital Supply Ground
Digital Supply Voltage (3.3V ± 5%)
Receive Loss of Signal Output
400 Hz Clock output for 64 kHz Operation
8 kHz clock output for 64 kHz Operation
Line Code Violation for 400 Hz
This pin will stay “High” when 400 Hz is not in sync.
Line Code Violation for 8 kHz in 64 kHz operation
Bipolar Violation:
In E1RZ or T1 mode, every Bipolar violation valid or not valid is indicated
at this pin.
This pin will stay “High” when 8 kHz is not in sync.
Receive Clock Violation.
In 64 kbps operation, every missing pulse will cause this pin to go “High”
for half the clock cycle
AIS Indication
In E1RZ or T1 mode, this output serves as an AIS indicator. AIS will stay
“High” for 250 µs in E1 RZ mode, and in T1 mode, AIS will stay “High” for
3 ms.
Data Invert:
Connect this pin “High” to output active “Low” data at RPOS/RNEG.
NOTE: Internally Pulled down with 50 kΩ resistor
Receive Clock Invert:
Connect this pin “High” to align the data to change at the falling edge of
RCLK.
NOTE: Internally Pulled down with 50 kΩ resistor
4
5 Page 
xr
REV. 1.0.2
XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
FIGURE 5. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1)
V1 nV V2 V1 V2 nV
(8 kHz)
(400 Hz)
(400 Hz)
LCV
125µs
(8 kHz)
125µs
(8 kHz)
125µs
(8 kHz)
125µs
(8 kHz)
if nV is
Missing
NOTES:
1. V1 and V2 indicate AMI code-rule violations, and give the 8kHz timing.
2. V1 and V2 have different violation polarity with respect to each other.
3. nV indicates no violation (violation stealing) and gives the 400 Hz timing.
1.2 2048 kHz RZ E1 Mode
In this mode, the XRT85L61 receives a standard E1 signal as shown in Figure 6. Table 4 gives the details of
the E1 pulse.
FIGURE 6. E1 PULSE MASK (G.703)
269 ns
(244 + 25 )
V = 100%
194 ns
(2 44 – 50 )
N o m in a l p u lse
50%
0%
244 ns
219 ns
(24 4 – 25)
488 ns
(24 4 + 244)
N ote – V corresponds to the nom inal peak value.
10
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet XRT85L61.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| XRT85L61 | BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR | Exar |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |