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PDF XR18W750 Data sheet ( Hoja de datos )
| Número de pieza | XR18W750 | |
| Descripción | WIRELESS UART CONTROLLER | |
| Fabricantes | Exar | |
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XR18W750
WIRELESS UART CONTROLLER
MARCH 2008
REV. 1.0.0
GENERAL DESCRIPTION
The XR18W750 is a Wireless UART Controller with a
two-wire I2C interface to the XR18W753 RF
transceiver to complete Exar’s Wireless UART
chipset solution. The XR18W750 supports both the
parallel and serial interfaces to any host system thus
providing flexibility for system designers to select
their interface option.
The XR18W750 includes an embedded 8051
microprocessor which provides the power to process
the protocol framing for data transmission and to
handle error processing. Internally, the XR18W750
has a 32KB system memory for loading the firmware
from an external EEPROM and for data processing.
The XR18W750 also includes a 128-bit AES engine
for data encoding and decoding.
The XR18W750 is available in a 48-pin QFN
package.
APPLICATIONS
• Industrial Automation
• Factory Automation
• Point of Sales Systems
• Industrial Servers
• Data Collection Terminals
FEATURES
• 2.25 to 3.63 Volt Operation
• 5 Volt Tolerant Inputs
• 8051 Microcontroller
• 32KB System Memory
• 128-bit AES Engine
• I2C Bus Master Interface to RF Transceivers
• Optional UART interface to RF Transceiver
• Selectable Serial or Parallel Mode Interface
• Enhanced UART
■ 16550 Compatible Register Set
■ Parallel mode data rate from 1200 bps to 230.4
Kbps
■ Serial mode data rate from 1200 bps to
921.6Kbps
■ Transmit and Receive FIFOs of 64 bytes
■ Programmable TX and RX FIFO Trigger Levels
■ Transmit and Receive FIFO Level Counters
■ Automatic Hardware (RTS/CTS) Flow Control
■ Selectable Auto RTS Flow Control Hysteresis
■ Full modem interface
• Device Identification and Revision
• 48-pin QFN package
FIGURE 1. XR18W750 BLOCK DIAGRAM
A2:A0
D7:D0
16/68#, CS#, IOW#, IOR#
INT, TXRDY#, RXRDY#
Parallel
Mode
TX, RX, RTS#, CTS#,
DTR#, DSR#, CD#, RI#
Serial
Mode
UART
AES
Encoding/
Decoding
32KB
System
Memory
8051
Microprocessor
I2C Interface
GPIO[3:0]
CLK+
CLK-
SDA
SCL
MODEM_RESET
RF_IRQ#
S/P#
RESET
RF_DI
RF_DO
EN_DIDO
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
1 page  
REV. 1.0.0
Pin Description
NAME
CLK-
CLK+
48-QFN
PIN #
3
4
XR18W750
WIRELESS UART CONTROLLER
TYPE
DESCRIPTION
I 16 MHz differential clock input or CMOS clock input. Use both signals for differ-
I ential clock.
GPIO[3:0]
TEST2
TEST1
TEST0
VCC
GND
Connect CLK- to VCC to enable the CMOS/TTL clock mode. The external
CMOS/TTL clock should be connected to CLK+.
13, 14, 15, I/O General Purpose I/O.
48
6 I Factor Test Modes (active high). For normal operation, connect these inputs to
7 I GND.
16 I
5, 25
Pwr 2.97V to 3.63V power supply.
2, 24
Pwr Power supply common, ground.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
5
5 Page 
XR18W750
REV. 1.0.0
WIRELESS UART CONTROLLER
3.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs to their default state (see
Table 15). An active high pulse of longer than 40 ns duration will be required to activate the reset function in
the device.
3.4 Device Identification and Revision
The XR18W750 has the same Device ID as the XR16L275x and XR16V275x. To read the identification code
from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now reading
the content of the DLM will provide 0x0A and reading the content of DLL will provide the revision of the part; for
example, a reading of 0x01 means revision A.
3.5 Internal Registers
The enhanced UART has a set of registers for control, monitoring and data loading and unloading. The
configuration register set is compatible to those already available in the standard single 16C550. These
registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO
control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers
(MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible Scratchpad
Register (SPR).
Beyond the general 16C550 features and capabilities, the XR18W750 offers enhanced feature registers
(EMSR, FLVL, EFR, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow control, FIFO trigger
level control, and FIFO level counters. All the register functions are discussed in full detail later in “Section 4.0,
UART INTERNAL REGISTERS” on page 18.
3.6 DMA Mode
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# and TXRDY# output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the enhanced UART is placed in single-character mode for data transmit or receive
operation. When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode,
the enhanced UART sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin
when the receive FIFO becomes empty. The following table shows their behavior. Also see Figures 16
through 21.
TABLE 3: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE
PINS
RXRDY#
FCR BIT-0=0
(FIFO DISABLED)
LOW = 1 byte.
HIGH = no data.
FCR BIT-0=1 (FIFO ENABLED)
FCR Bit-3 = 0
(DMA Mode Disabled)
LOW = at least 1 byte in FIFO.
HIGH = FIFO empty.
FCR Bit-3 = 1
(DMA Mode Enabled)
HIGH to LOW transition when FIFO reaches the
trigger level, or time-out occurs.
LOW to HIGH transition when FIFO empties.
TXRDY# LOW = THR empty. LOW = FIFO empty.
LOW = FIFO has at least 1 empty location.
HIGH = byte in THR. HIGH = at least 1 byte in FIFO. HIGH = FIFO is full.
11
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