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PDF THC63LVD103D Data sheet ( Hoja de datos )
| Número de pieza | THC63LVD103D | |
| Descripción | 160MHz 30bit COLOR LVDS TRANSMITTER | |
| Fabricantes | THine Electronics | |
| Logotipo |  |
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THC63LVD103D_Rev.4.01_E
THC63LVD103D
160MHz 30bit COLOR LVDS TRANSMITTER
General Description
The THC63LVD103D transmitter is designed to support pixel
data transmission between Host and Flat Panel Display from
NTSC up to 1080p(60Hz) .
The THC63LVD103D converts 35bits of CMOS/TTL data into
four LVDS data streams. The transmitter can be programmed
for rising edge or falling edge clock through a dedicated pin.
At a transmit clock frequency of 160MHz, 30bits of RGB data
and 5bits of timing and control data (HSYNC, VSYNC, DE,
CONT1) are transmitted at an effective rate of 1120Mbps per
LVDS channel.
Application
･Medium and Small Size Panel
･Tablet PC / Notebook PC
･Security Camera / Industrial Camera
･Multi Function Printer
･Industrial Equipment
･Medical Equipment Monitor
Features
･Compatible with TIA/EIA-644 LVDS Standard
･7:1 LVDS Transmitter
･Operating Temperature Range : 0 to +70C
･No Special Start-up Sequence Required
･Spread Spectrum Clocking Tolerant up to 100kHz Frequency
Modulation and +/-2.5% Deviations.
･Wide Dot Clock Range: 8 to 160MHz Suited for
TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)
PC Signal : QVGA(8MHz) - WUXGA(154MHz)
･64pin TQFP Package
･1.2V to 3.3V LVCMOS/ inputs are supported.
･LVDS swing is reducible as 200mV by RS-pin to reduce EMI
and power consumption.
･PLL requires no external components.
･Power Down Mode.
･Input clock triggering edge is selectable by R/F-pin
･EU RoHS Compliant.
Block Diagram
Figure 1. Block Diagram
Copyright©2015 THine Electronics, Inc.
1
THine Electronics, Inc.
1 page  
THC63LVD103D_Rev.4.01_E
Power Consumption
Symbol
Over recommended operating supply and temperature range unless otherwise specified
Parameter
Conditions
Typ* Max Unit
ITCCW
LVDS Transmitter
Operating Current
Worst Case Pattern
(Fig.5)
RL=100, CL=5pF, f=85MHz, RS=VCC
RL=100, CL=5pF, f=135MHz, RS=VCC
RL=100, CL=5pF, f=160MHz, RS=VCC
LVDS Transmitter
Operating Current
Worst Case Pattern
(Fig.5)
RL=100, CL=5pF, f=85MHz, RS=GND
RL=100, CL=5pF, f=160MHz, RS=GND
RL=100, CL=5pF, f=160MHz, RS=GND
ITCCS
LVDS Transmitter
Power Down Current
/PDWN=L, All Inputs=L or H
*Typ values are at the conditions of VCC=3.3V and Ta = +25ºC
69
87
97
55
73
83
-
75 mA
93 mA
104 mA
61 mA
79 mA
89 mA
10 µA
Table 4. Power Consumption
Worst Case Pattern
CLKIN
Tx0-6
x=A,B,C,D
Figure 4. Worst Case Pattern
Copyright©2015 THine Electronics, Inc.
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THine Electronics, Inc.
5 Page 
THC63LVD103D_Rev.4.01_E
LVDS Data Timing Diagram
Figure 12. LVDS Data Timing Diagram
THC63LVD103D Pixel Data Mapping for JEIDA Format (6bit, 8bit and 10bit Application)
6bit 8bit 10bit
TA0 R4 R4 R4
TA1 R5 R5 R5
TA2 R6 R6 R6
TA3 R7 R7 R7
TA4 R8 R8 R8
TA5 R9 R9 R9
TA6 G4 G4 G4
TB0 G5 G5 G5
TB1 G6 G6 G6
TB2 G7 G7 G7
TB3 G8 G8 G8
TB4 G9 G9 G9
TB5 B4 B4 B4
TB6 B5 B5 B5
TC0 B6 B6 B6
TC1 B7 B7 B7
TC2 B8 B8 B8
TC3 B9 B9 B9
TC4
Hsync
Hsync
Hsync
TC5
Vsync
Vsync
Vsync
TC6 DE DE DE
TD0 - R2 R2
TD1 - R3 R3
TD2 - G2 G2
TD3 - G3 G3
TD4 - B2 B2
TD5 - B3 B3
TD6 - N/A N/A
TE0 -
- R0
TE1 -
- R1
TE2 -
- G0
TE3 -
- G1
TE4 -
- B0
TE5 -
- B1
TE6 -
- N/A
Note : Use TA to TC channels and open TD channel for 6bit application.
Use TA to TD channels and open TE channel for 8bit application.
Table 8. Data Mapping for JEIDA Format
Copyright©2015 THine Electronics, Inc.
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THine Electronics, Inc.
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet THC63LVD103D.PDF ] | |
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