DataSheet.es    


PDF CY14E256LA Data sheet ( Hoja de datos )

Número de pieza CY14E256LA
Descripción 256-Kbit (32 K x 8) nvSRAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



Hay una vista previa y un enlace de descarga de CY14E256LA (archivo pdf) en la parte inferior de esta página.


Total 19 Páginas

No Preview Available ! CY14E256LA Hoja de datos, Descripción, Manual

CY14E256LA
256-Kbit (32 K × 8) nvSRAM
256-Kbit (32 K × 8) nvSRAM
Features
25 ns and 45 ns access times
Internally organized as 32 K × 8 (CY14E256LA)
Hands-off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements initiated by
software, device pin, or autostore on power-down
RECALL to SRAM initiated by software or power-up
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20-year data retention
Single 5 V + 10% operation
Industrial temperature
44-pin thin small-outline package (TSOP) Type II and 32-pin
small-outline integrated circuit (SOIC) package
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14E256LA is a fast static RAM, with a
nonvolatile element in each memory cell. The memory is
organized as 32 KB. The embedded nonvolatile elements
incorporate QuantumTrap technology, producing the world’s
most reliable nonvolatile memory. The SRAM provides infinite
read and write cycles, while independent nonvolatile data
resides in the highly reliable QuantumTrap cell. Data transfers
from the SRAM to the nonvolatile elements (the STORE
operation) takes place automatically at power-down. On
power-up, data is restored to the SRAM (the RECALL operation)
from the nonvolatile memory. Both the STORE and RECALL
operations are also available under software control.
For a complete list of related documentation, click here.
Logic Block Diagram
A5
A6
A7
A8
A9
A 11
A 12
A 13
A 14
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
QuantumTrap
512 X 512
STORE
STATIC RAM
ARRAY
512 X 512
RECALL
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
VCC
VCAP
POWER
CONTROL
STORE/
RECALL
CONTROL
HSB
SOFTWARE
DETECT
-A13 A0
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-54952 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 14, 2014

1 page




CY14E256LA pdf
CY14E256LA
During any STORE operation, regardless of how it is initiated,
the CY14E256LA continues to drive the HSB pin LOW, releasing
it only when the STORE is complete. Upon completion of the
STORE operation, the nvSRAM memory access is inhibited for
tLZHSB time after HSB pin returns HIGH. Leave the HSB
unconnected if it is not used.
Hardware RECALL (Power-up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the sense voltage of VSWITCH, a RECALL
cycle is automatically initiated and takes tHRECALL to complete.
During this time, HSB is driven low by the HSB driver.
Software STORE
Data is transferred from SRAM to the nonvolatile memory by a
software address sequence. The CY14E256LA Software
STORE cycle is initiated by executing sequential CE or OE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from nonvolatile memory to the SRAM by a
software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read address 0x0E38 Valid READ
2. Read address 0x31C7 Valid READ
3. Read address 0x03E0 Valid READ
4. Read address 0x3C1F Valid READ
5. Read address 0x303F Valid READ
6. Read address 0x0C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Table 1. Mode Selection
CE WE
HX
LH
LL
LH
OE
A14–A0[6]
Mode
I/O Power
X
X
Not selected Output high Z
Standby
L
X
Read SRAM
Output data
Active
X
X
Write SRAM
Input data
Active
L
0x0E38
Read SRAM
Output data
Active[7]
0x31C7
Read SRAM
Output data
0x03E0
Read SRAM
Output data
0x3C1F
Read SRAM
Output data
0x303F
Read SRAM
Output data
0x0B45
AutoStore
Output data
disable
Notes
6. While there are 15 address lines on the CY14E256LA, only the lower 14 are used to control software modes.
7. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
Document Number: 001-54952 Rev. *K
Page 5 of 19

5 Page





CY14E256LA arduino
Switching Waveforms (continued)
Figure 5. SRAM Read Cycle #2 (CE and OE Controlled) [21, 22]
Address
CE
OE
Data Output
ICC
Address
Address Valid
tACE
tRC
tHZCE
tAA
tLZCE
tDOE
tHZOE
High Impedance
tLZOE
tPU
Output Data Valid
tPD
Standby
Active
Figure 6. SRAM Write Cycle #1 (WE Controlled) [22, 23, 24]
tWC
Address Valid
tSCE
tHA
CE
WE
Data Input
Data Output
tAW
tPWE
tSA
tSD tHD
tHZWE
Input Data Valid
tLZWE
Previous Data
High Impedance
Figure 7. SRAM Write Cycle #2 (CE Controlled) [22, 23, 24]
tWC
Address
Address Valid
tSA tSCE
tHA
CE
tPWE
WE
tSD tHD
Data Input
Input Data Valid
Data Output
High Impedance
Note
21. WE must be HIGH during SRAM read cycles.
22. HSB must remain HIGH during READ and WRITE cycles.
23. If WE is low when CE goes low, the outputs remain in the high impedance state.
24. CE or WE must be > VIH during address transitions.
Document Number: 001-54952 Rev. *K
CY14E256LA
Page 11 of 19

11 Page







PáginasTotal 19 Páginas
PDF Descargar[ Datasheet CY14E256LA.PDF ]




Hoja de datos destacado

Número de piezaDescripciónFabricantes
CY14E256L256-Kbit (32K x 8) nvSRAMCypress Semiconductor
Cypress Semiconductor
CY14E256LA256-Kbit (32 K x 8) nvSRAMCypress Semiconductor
Cypress Semiconductor

Número de piezaDescripciónFabricantes
SLA6805M

High Voltage 3 phase Motor Driver IC.

Sanken
Sanken
SDC1742

12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.

Analog Devices
Analog Devices


DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.


DataSheet.es    |   2020   |  Privacy Policy  |  Contacto  |  Buscar