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PDF S34ML08G2 Data sheet ( Hoja de datos )
| Número de pieza | S34ML08G2 | |
| Descripción | x8 I/O and 3 V VCC NAND Flash Memory | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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S34ML08G2
8 Gb, 4-bit ECC, x8 I/O and 3 V VCC
NAND Flash Memory for Embedded
Distinctive Characteristics
Density
– 8 Gb (4 Gb x 2)
Architecture (For each 4 Gb device)
– Input / Output Bus Width: 8-bits
– Page Size: (2048 + 128) bytes; 128-byte spare area
– Block Size: 64 Pages or (128k + 8k) bytes
– Plane Size
– 2048 Blocks per Plane or (256M + 16M) bytes
– Device Size
– 2 Planes per Device or 512 Mbyte
NAND Flash Interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply Voltage
– 3.3V device: Vcc = 2.7V ~ 3.6V
Performance
Page Read / Program
– Random access: 30 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 300 µs (Typ)
Block Erase / Multiplane Erase
– Block Erase time: 3.5 ms (Typ)
Security
– One Time Programmable (OTP) area
– Serial number (unique ID)
– Hardware program/erase disabled during power transition
Additional Features
– Supports Multiplane Program and Erase commands
– Supports Copy Back Program
– Supports Multiplane Copy Back Program
– Supports Read Cache
Electronic Signature
– Manufacturer ID: 01h
Operating Temperature
– Industrial: -40°C to 85°C
– industrial Plus: -40°C to 105°C
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 4-bit ECC per 528 bytes)
– 10 Year Data retention (Typ)
– Blocks zero and one are valid and will be valid for at least 1000
program-erase cycles with ECC
Package Options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 x 20 x 1.2 mm
– 63-Ball BGA 11 x 9 x 1 mm
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00484 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised Monday, April 25, 2016
1 page  
S34ML08G2
4. Block Diagrams
Figure 4.1 Functional Block Diagram — 8 Gb
Address
Register/
Counter
Program Erase
Controller
HV Generation
ALE
CLE
WE#
CE#
WP#
RE#
Command
Interface
Logic
Command
Register
Data
Register
8192 Mbit + 512 Mbit (8 Gb Device)
NAND Flash
Memory Array
X
D
E
C
O
D
E
R
Page Buffer
Y Decoder
I/O Buffer
I/O0~I/O7
Document Number: 002-00484 Rev. *F
Page 5 of 16
5 Page 
S34ML08G2
8.3 DC Characteristics
Table 8.3 DC Characteristics and Operating Conditions
Parameter
Symbol
Test Conditions
Min
Typ
Max
Units
Power On Current
ICC0
FFh command input
after power on
—
—
50 per
device
mA
Operating Current
Sequential Read
ICC1
tRC = tRC (min)
CE# = VIL, Iout = 0 mA
—
15
30 mA
Program
Normal
— 15 30 mA
ICC2 Cache — 15 30 mA
Standby Current, (TTL)
Erase
ICC3 — — 15 30 mA
ICC4
CE# = VIH,
——
WP# = 0V/Vcc
1 mA
Standby Current, (CMOS)
Input Leakage Current
Output Leakage Current
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Output Low Current (R/B#)
Erase and Program Lockout Voltage
ICC5
CE# = VCC-0.2,
WP# = 0/VCC
—
10
50
µA
ILI
VIN = 0 to VCC(max)
—
— ±10 µA
ILO
VOUT = 0 to VCC(max)
—
— ±10 µA
VIH — VCC x 0.8 — VCC + 0.3 V
VIL — -0.3 — VCC x 0.2 V
VOH
IOH = -400 µA
2.4 —
—
V
VOL IOL = 2.1 mA — — 0.4 V
IOL(R/B#)
VOL = 0.4V
8 10 — mA
VLKO
—
— 1.8 —
V
Notes:
1. All VCC pins, and VSS pins respectively, are shorted together.
2. Values listed in this table refer to the complete voltage range for VCC and to a single device in case of device stacking.
3. All current measurements are performed with a 0.1 µF capacitor connected between the VCC Supply Voltage pin and the VSS Ground pin.
4. Standby current measurement can be performed after the device has completed the initialization process at power up.
8.4 Pin Capacitance
Table 8.4 Pin Capacitance (TA = 25°C, f=1.0 MHz)
Parameter
Symbol
Test Condition
Min
Max
Unit
Input
Input / Output
CIN
VIN = 0V
— 10 pF
CIO
VIL = 0V
— 10 pF
Note:
1. For the stacked devices version the Input is 10 pF x [number of stacked chips] and the Input/Output is 10 pF x [number of stacked chips].
8.5 Power Consumptions and Pin Capacitance for Allowed Stacking
Configurations
When multiple dies are stacked in the same package, the power consumption of the stack will increase according to the number of
chips. As an example, the standby current is the sum of the standby currents of all the chips, while the active power consumption
depends on the number of chips concurrently executing different operations.
When multiple dies are stacked in the same package the pin/ball capacitance for the single input and the single input/output of the
combo package must be calculated based on the number of chips sharing that input or that pin/ball.
Document Number: 002-00484 Rev. *F
Page 11 of 16
11 Page | ||
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| PDF Descargar | [ Datasheet S34ML08G2.PDF ] | |
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