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PDF S34ML04G1 Data sheet ( Hoja de datos )

Número de pieza S34ML04G1
Descripción 3V SLC NAND Flash
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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Distinctive Characteristics
Density
– 1 Gb/ 2 Gb / 4 Gb
Architecture
– Input / Output Bus Width: 8-bits / 16-bits
– Page size:
– x8 = 2112 (2048 + 64) bytes; 64 bytes is spare area
– x16 = 1056 (1024 + 32) words; 32 words is spare area
– Block size: 64 Pages
– x8 = 128 KB + 4 KB
– x16 = 64k + 2k words
– Plane size:
– 1 Gb / 2 Gb: 1024 Blocks per Plane
x8 = 128 MB + 4 MB
x16 = 64M + 2M words
– 4 Gb: 2048 Blocks per Plane
x8 = 256 MB+ 8 MB
x16 = 128M + 4M words
– Device size:
– 1 Gb: 1 Plane per Device or 128 MB
– 2 Gb: 2 Planes per Device or 256 MB
– 4 Gb: 2 Planes per Device or 512 MB
Performance
Page Read / Program
– Random access: 25 µs (Max)
– Sequential access: 25 ns (Min)
– Program time / Multiplane Program time: 200 µs (Typ)
Block Erase (S34ML01G1)
– Block Erase time: 2.0 ms (Typ)
Block Erase / Multiplane Erase (S34ML02G1, S34ML04G1)
– Block Erase time: 3.5 ms (Typ)
S34ML01G1
S34ML02G1, S34ML04G1
1 Gb, 2 Gb, 4 Gb, 3 V SLC
NAND Flash For Embedded
NAND flash interface
– Open NAND Flash Interface (ONFI) 1.0 compliant
– Address, Data and Commands multiplexed
Supply voltage
– 3.3-V device: Vcc = 2.7 V ~ 3.6 V
Security
– One Time Programmable (OTP) area
– Hardware program/erase disabled during power transition
Additional features
– 2 Gb and 4 Gb parts support Multiplane Program and Erase
commands
– Supports Copy Back Program
– 2 Gb and 4 Gb parts support Multiplane Copy Back Program
– Supports Read Cache
Electronic signature
– Manufacturer ID: 01h
Operating temperature
– Industrial: -40 °C to 85 °C
– Automotive: -40 °C to 105 °C
Reliability
– 100,000 Program / Erase cycles (Typ)
(with 1 bit ECC per 528 bytes (x8) or 264 words (x16))
– 10 Year Data retention (Typ)
– For one plane structure (1-Gb density)
– Block zero is valid and will be valid for at least 1,000 program-
erase cycles with ECC
– For two plane structures (2-Gb and 4-Gb densities)
– Blocks zero and one are valid and will be valid for at least
1,000 program-erase cycles with ECC
Package options
– Lead Free and Low Halogen
– 48-Pin TSOP 12 x 20 x 1.2 mm
– 63-Ball BGA 9 x 11 x 1 mm
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00676 Rev. *S
• San Jose, CA 95134-1709 • 408-943-2600
Revised Wednesday, August 31, 2016

1 page




S34ML04G1 pdf
S34ML01G1
S34ML02G1, S34ML04G1
1.2
Connection Diagram
Figure 1.2 48-Pin TSOP1 Contact ×8, ×16 Devices
x16 x8
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
R/B#
RE#
CE#
NC
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
1
12
13
24
NAND Flash
TSOP1
x8 x16
48 VSS (1) VSS
NC I/O15
NC I/O14
NC I/O13
I/O7 I/O7
I/O6 I/O6
I/O5 I/O5
I/O4 I/O4
NC I/O12
VCC(1) VCC
NC NC
37 VCC VCC
36 VSS VSS
NC NC
VCC(1) VCC
NC I/011
I/O3 I/O3
I/O2 I/O2
I/O1 I/O1
I/O0 I/O0
NC I/O10
NC I/O9
NC I/O8
25 VSS (1) VSS
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Figure 1.3 63-BGA Contact, ×8 Device (Balls Down, Top View)
A1 A2
NC NC
A9 A10
NC NC
B1 B9 B10
NC NC NC
C3 C4 C5 C6 C7 C8
WP#
ALE
VSS
CE#
WE#
RB#
D3
VCC (1)
D4
RE#
D5
CLE
D6
NC
D7 D8
NC NC
E3 E4 E5 E6 E7 E8
NC NC NC NC NC NC
F3 F4 F5 F6 F7 F8
NC NC NC NC VSS (1) NC
G3 G4 G5 G6 G7 G8
NC VCC (1) NC NC NC NC
H3 H4 H5 H6 H7 H8
NC I/O0 NC NC NC Vcc
J3 J4 J5 J6 J7 J8
NC I/O1 NC VCC I/O5 I/O7
K3 K4 K5 K6 K7 K8
VSS I/O2 I/O3 I/O4 I/O6 VSS
L1 L2
NC NC
L9 L10
NC NC
M1 M2
NC NC
M9 M10
NC NC
Note:
1. These pins should be connected to power supply or ground (as designated) following the ONFI specification, however they might not be bonded internally.
Document Number: 002-00676 Rev. *S
Page 5 of 73

5 Page





S34ML04G1 arduino
S34ML01G1
S34ML02G1, S34ML04G1
1.6.3
S34ML04G1
Table 1.5 Address Cycle Map — 4 Gb Device
Bus Cycle I/O [15:8] (6) I/O0 I/O1 I/O2
I/O3 I/O4 I/O5 I/O6 I/O7
×8
1st / Col. Add. 1
A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
A8 (CA8) A9 (CA9) A10 (CA10) A11 (CA11) Low
Low
Low
Low
3rd / Row Add. 1
A12 (PA0) A13 (PA1) A14 (PA2) A15 (PA3) A16 (PA4) A17 (PA5)
A18
(PLA0)
A19 (BA0)
4th / Row Add. 2 — A20 (BA1) A21 (BA2) A22 (BA3) A23 (BA4) A24 (BA5) A25 (BA6) A26 (BA7) A27 (BA8)
5th / Row Add. 3
A28 (BA9)
A29
(BA10)
Low
Low Low Low Low Low
×16
1st / Col. Add. 1
Low
A0 (CA0) A1 (CA1) A2 (CA2) A3 (CA3) A4 (CA4) A5 (CA5) A6 (CA6) A7 (CA7)
2nd / Col. Add. 2
Low
A8 (CA8) A9 (CA9) A10 (CA10)
Low
Low Low Low Low
3rd / Row Add. 1
Low
A11 (PA0) A12 (PA1) A13 (PA2) A14 (PA3) A15 (PA4) A16 (PA5)
A17
(PLA0)
A18 (BA0)
4th / Row Add. 2 Low A19 (BA1) A20 (BA2) A21 (BA3) A22 (BA4) A23 (BA5) A24 (BA6) A25 (BA7) A26 (BA8)
5th / Row Add. 3
Low
A27 (BA9)
A28
(BA10)
Low
Low Low Low Low Low
Notes:
1. CAx = Column Address bit.
2. PAx = Page Address bit.
3. PLA0 = Plane Address bit zero.
4. BAx = Block Address bit.
5. Block address concatenated with page address and plane address = actual page address, also known as the row address.
6. I/O[15:8] are not used during the addressing sequence and should be driven Low.
For the ×8 address bits, the following rules apply:
A0 - A11: column address in the page
A12 - A17: page address in the block
A18: plane address (for multiplane operations) / block address (for normal operations)
A19 - A29: block address
For the ×16 address bits, the following rules apply:
A0 - A10: column address in the page
A11 - A16: page address in the block
A17: plane address (for multiplane operations) / block address (for normal operations)
A18 - A28: block address
Document Number: 002-00676 Rev. *S
Page 11 of 73

11 Page







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