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PDF CY14V116N Data sheet ( Hoja de datos )

Número de pieza CY14V116N
Descripción 16-Mbit (1024 K x 16) nvSRAM
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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CY14V116N
16-Mbit (1024 K × 16) nvSRAM
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
30-ns and 45-ns access times
Logically organized as 1024 K × 16
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 650 A
Sleep mode current of 10 A
Operating voltage
Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.65 V to 1.95 V
Industrial temperature: –40 C to +85 C
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14V116N is a fast SRAM, with a nonvolatile
element in each memory cell. The memory is organized as
1024 K words of 16 bits each. The embedded nonvolatile
elements incorporate QuantumTrap technology, producing the
world’s most reliable nonvolatile memory. The SRAM can be
read and written an infinite number of times. The nonvolatile data
residing in the nonvolatile elements do not change when data is
written to the SRAM. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power-down. On power-up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
For a complete list of related documentation, click here.
Logic Block Diagram
A0-A11
QUANTUMTRAP
4096 X 4096
STORE
STATIC RAM
ARRAY
4096 X 4096
RECALL
VCC VCAP VCCQ
POWER CONTROL
SLEEP MODE
CONTROL
ZZ
STORE / RECALL
CONTROL
HSB
SOFTWARE
DETECT
A2-A14
OE
CE
WE
[1]
DQ 0-DQ 15
COLUMN IO
COLUMN DECODER
BLE
BHE
ZZ
A12-A19
Note
1. In this datasheet, CE refers to the internal logical combination of CE1 and CE2, such that when CE1 is LOW and CE2 is HIGH, CE is LOW. For all other cases CE is HIGH.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-75791 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015

1 page




CY14V116N pdf
CY14V116N
Device Operation
The CY14V116N nvSRAM is made up of two functional
components paired in the same physical cell. These are an
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation) automatically at power-down, or from the nonvolatile
cell to the SRAM (the RECALL operation) on power-up. Both the
STORE and RECALL operations are also available under
software control. Using this unique architecture, all cells are
stored and recalled in parallel. During the STORE and RECALL
operations, SRAM read and write operations are inhibited. The
CY14V116N supports infinite reads and writes to the SRAM. In
addition, it provides infinite RECALL operations from the
nonvolatile cells and up to 1 million STORE operations. See the
Truth Table For SRAM Operations on page 20 for a complete
description of read and write modes.
SRAM Read
The CY14V116N performs a read cycle whenever CE and OE
are LOW, and WE, ZZ, and HSB are HIGH. The address
specified on pins A0–A19 determines which of the 1,048,576
words of 16 bits each are accessed. Byte enables (BHE, BLE)
determine which bytes are enabled to the output. When the read
is initiated by an address transition, the outputs are valid after a
delay of tAA (read cycle 1). If the read is initiated by CE or OE,
the outputs are valid at tACE or at tDOE, whichever is later (read
cycle 2). The data output repeatedly responds to address
changes within the tAA access time without the need for
transitions on any control input pins. This remains valid until
another address change or until CE or OE is brought HIGH, or
WE or HSB is brought LOW.
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
the end of the cycle. The data on the common I/O pins
DQ0–DQ15 is written into the memory if it is valid tSD before the
end of a WE-controlled write or before the end of a CE-controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written. Keep OE HIGH during the entire write cycle to avoid
data bus contention on common I/O lines. If OE is left LOW, the
internal circuitry turns off the output buffers tHZWE after WE goes
LOW.
AutoStore Operation (Power-Down)
The CY14V116N stores data to the nonvolatile QuantumTrap
cells using one of the three storage operations. These three
operations are: Hardware STORE, activated by the HSB;
Software STORE, activated by an address sequence; AutoStore,
on device power-down. The AutoStore operation is a unique
feature of nvSRAM and is enabled by default on the CY14V116N
device.
During normal operation, the device draws current from VCC to
charge a capacitor connected to the VCAP pin. This stored
charge is used by the chip to perform a STORE operation during
power-down. If the voltage on the VCC pin drops below VSWITCH,
the part automatically disconnects the VCAP pin from VCC and a
STORE operation is initiated with power provided by the VCAP
capacitor.
Note If the capacitor is not connected to the VCAP pin, AutoStore
must be disabled using the soft sequence specified in the section
Preventing AutoStore on page 9. If AutoStore is enabled without
a capacitor on the VCAP pin, the device attempts an AutoStore
operation without sufficient charge to complete the STORE. This
corrupts the data stored in the nvSRAM.
Figure 2. AutoStore Mode
VCCQ VCC
0.1uF
VCCQ VCC
0.1uF
WE VCAP
VSS
VCAP
Figure 2 shows the proper connection of the storage capacitor
(VCAP) for automatic STORE operation. Refer to DC Electrical
Characteristics on page 10 for the size of the VCAP. The voltage
on the VCAP pin is driven to VVCAP by a regulator on the chip. A
pull-up resistor should be placed on WE to hold it inactive during
power-up. This pull-up resistor is only effective if the WE signal
is in tristate during power-up. When the nvSRAM comes out of
power-up-RECALL, the host microcontroller must be active or
the WE held inactive until the host microcontroller comes out of
reset.
To reduce unnecessary nonvolatile STOREs, AutoStore and
Hardware STORE operations are ignored unless at least one
write operation has taken place (which sets a write latch) since
the most recent STORE or RECALL cycle. Software initiated
STORE cycles are performed regardless of whether a write
operation has taken place.
Document #: 001-75791 Rev. *H
Page 5 of 25

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CY14V116N arduino
CY14V116N
DC Electrical Characteristics (continued)
Over the Operating Range
Parameter
Description
IIX[8]
Input leakage current
(except HSB)
Test Conditions
VCC = VCC (max), VSS < VIN < VCC
Min
Typ[6]
Max
Unit
–1 – +1 A
Input leakage current (for VCC = VCC (max), VSS < VIN < VCC
HSB)
–100
+1 A
IOZ
Off state output leakage VCC = VCC (max), VSS < VOUT < VCC, CE or OE >
–1
– +1 A
current
VIH or BLE/BHE > VIH or WE < VIL
VIH Input HIGH voltage
VIL Input LOW voltage
VOH
Output HIGH voltage
IOUT = –1 mA
VOL
Output LOW voltage
IOUT = 2 mA
VCAP[9]
Storage capacitor
Between VCAP pin and VSS
VVCAP[10, 11] Maximum voltage driven VCC = VCC (max)
on VCAP pin by the device
0.7 × VCCQ
Vss – 0.3
VCCQ – 0.45
19.8
22.0
VCCQ + 0.3
0.3 × VCCQ
0.45
82.0
5.0
V
V
V
V
F
V
Data Retention and Endurance
Over the Operating Range
Parameter
DATAR
NVC
Description
Data retention
Nonvolatile STORE operations
Min
20
1,000,000
Unit
Years
Cycles
Capacitance
In the following table, the capacitance parameters are listed. [11]
Parameter
CIN
CIO
COUT
Description
Input capacitance
Input/Output capacitance
Output capacitance
Test Conditions
TA = 25 C, f = 1 MHz,
VCC = VCC (typ), VCCQ = VCCQ (typ)
Max
10
10
10
Unit
pF
pF
pF
Thermal Resistance
In the following table, the thermal resistance parameters are listed.[11]
Parameter
JA
JC
Description
Thermal resistance
(Junction to ambient)
Thermal resistance
(Junction to case)
Test Conditions
Test conditions follow standard test
methods and procedures for
measuring thermal impedance, in
accordance with EIA/JESD51.
165-FBGA
15.6
2.9
Unit
C/W
C/W
Notes
8. The HSB pin has IOUT = -4 uA for VOH of 1.07 V when both active HIGH and LOW drivers are disabled. When they are enabled standard VOH and VOL are valid. This
parameter is characterized but not tested
9. Min VCAP value guarantees that there is a sufficient charge available to complete a successful AutoStore operation. Max VCAP value guarantees that the capacitor on
VCAP is charged to a minimum voltage during a Power-Up RECALL cycle so that an immediate power-down cycle can complete a successful AutoStore. Therefore, it
is always recommended to use a capacitor within the specified min and max limits.
10. Maximum voltage on VCAP pin (VVCAP) is provided for guidance when choosing the VCAP capacitor. The voltage rating of the VCAP capacitor across the operating
temperature range should be higher than the VVCAP voltage
11. These parameters are only guaranteed by design and are not tested.
Document #: 001-75791 Rev. *H
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