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PDF CY14B116M Data sheet ( Hoja de datos )

Número de pieza CY14B116M
Descripción 16-Mbit (2048 K x 8/1024 K x 16) nvSRAM
Fabricantes Cypress Semiconductor 
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CY14B116K/CY14B116M
16-Mbit (2048 K × 8/1024 K × 16) nvSRAM with
Real Time Clock
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
25-ns and 45-ns access times
Internally organized as 2048 K × 8 (CY14B116K),
1024 K × 16 (CY14B116M)
Hands-off automatic STORE on power-down with only a
small capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, device pin, or AutoStore on power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years
Sleep mode operation
Full-featured real time clock (RTC)
Watchdog timer
Clock alarm with programmable interrupts
Backup power fail indication
Square wave output with programmable frequency
(1 Hz, 512 Hz, 4096 Hz, 32.768 kHz)
Capacitor or battery backup for RTC
Backup current of 0.45 A (typical)
Low power consumption
Active current of 75 mA at 45 ns
Standby mode current of 750 A
Sleep mode current of 10 A
Operating voltage: VCC = 2.7 V to 3.6 V
Industrial temperature: –40 C to +85 C
Packages
44-pin thin small-outline package (TSOP II)
54-pin thin small-outline package (TSOP II)
165-ball fine-pitch ball grid array (FBGA) package
Restriction of hazardous substances (RoHS) compliant
Functional Description
The Cypress CY14B116K/CY14B116M combines a 16-Mbit
nvSRAM with a full-featured RTC in a monolithic integrated
circuit. The nvSRAM is a fast SRAM with a nonvolatile element
in each memory cell. The memory is organized as 2048 K bytes
of 8 bits each or 1024 K words of 16 bits each. The embedded
nonvolatile elements incorporate the QuantumTrap technology,
producing the world’s most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data residing in the nonvolatile elements do not
change when data is written to the SRAM. Data transfers from
the SRAM to the nonvolatile elements (the STORE operation)
takes place automatically at power-down. On power-up, data is
restored to the SRAM (the RECALL operation) from the
nonvolatile memory. Both the STORE and RECALL operations
are also available under software control.
The RTC function provides an accurate clock with leap year
tracking and a programmable, high-accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-67786 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015

1 page




CY14B116M pdf
CY14B116K/CY14B116M
Table 1. Pin Definitions
Pin Name I/O Type
Description
A0–A20
A0–A19
DQ0–DQ7
DQ0–DQ15
Input
Address inputs. Used to select one of the 2,097,152 bytes of the nvSRAM for the ×8 configuration.
Address inputs. Used to select one of the 1,048,576 words of the nvSRAM for the ×16 configuration.
Input/Output
Bidirectional data I/O lines for the ×8 configuration. Used as input or output lines depending on
operation.
Bidirectional data I/O lines for the ×16 configuration. Used as input or output lines depending on
operation.
WE
Input
Write Enable input, Active LOW. When selected LOW, data on the I/O pins is written to the specific
address location.
CE
CE1, CE2
OE
Input
Input
Chip Enable input in TSOP II package, Active LOW. When LOW, selects the chip. When HIGH,
deselects the chip.
Chip Enable input in FBGA package. The device is selected and a memory access begins on the
falling edge of CE1 (while CE2 is HIGH) or the rising edge of CE2 (while CE1 is LOW).
Output Enable, Active LOW. The Active LOW OE input enables the data output buffers during read
cycles. Deasserting OE HIGH causes the I/O pins to tristate.
BLE
BHE
ZZ[6]
Input
Input
Input
Byte Enable, Active LOW. When selected LOW, enables DQ7–DQ0.
Byte Enable, Active LOW. When selected LOW, enables DQ15–DQ8.
Sleep Mode Enable. When the ZZ pin is pulled LOW, the device enters a low-power Sleep mode and
consumes the lowest power. Since this input is logically AND’ed with CE, ZZ must be HIGH for normal
operation.
Xout[7]
Output Crystal connection. Drives crystal on start-up.
Xin[7]
Input
Crystal connection. For 32.768-KHz crystal.
VRTCcap[7] Power Supply Capacitor supplied backup RTC supply voltage. Left unconnected if VRTCbat is used.
VRTCbat[7] Power Supply Battery supplied backup RTC supply voltage. Left unconnected if VRTCcap is used.
INT[7]
Output
Interrupt output/calibration/square wave. Programmable to respond to the clock alarm, the watchdog
timer, and the power monitor. In addition, programmable to be either Active HIGH (push or pull) or LOW
(open drain). In the Calibration mode, a 512-Hz square wave is driven out. In the Square Wave mode,
you can select a frequency of 1 Hz, 512 Hz, 4,096 Hz, or 32,768 Hz to be used as a continuous output.
VCC
VSS
HSB
Power Supply Power supply inputs to the device.
Power Supply Ground for the device. Must be connected to ground of the system.
Input/Output
Hardware STORE Busy (HSB).When LOW, this output indicates that a Hardware STORE is in
progress. When pulled LOW external to the chip, it initiates a nonvolatile STORE operation. After each
Hardware and Software STORE operation, HSB is driven HIGH for a short time (tHHHD) with standard
output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor
connection optional).
VCAP
Power Supply
AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
nonvolatile elements.
NC NC No Connect. Die pads are not connected to the package pin.
Notes
6. Sleep mode feature is offered only in the 165-ball FBGA package.
7. Left unconnected if RTC feature is not used.
Document #: 001-67786 Rev. *J
Page 5 of 42

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CY14B116M arduino
CY14B116K/CY14B116M
Using a capacitor has the obvious advantage of recharging the
backup source each time the system is powered up. If a battery
is used, a 3-V lithium battery is recommended and the
CY14B116K sources current only from the battery when the
primary power is removed. However, the battery is not recharged
at any time by the CY14B116K. The battery capacity must be
chosen for total anticipated cumulative down time required over
the life of the system.
Stopping and Starting the Oscillator
The OSCEN bit in the calibration register at 0x1FFFF8 controls
enabling and disabling of the oscillator. This bit is nonvolatile and
is shipped to customers in the “enabled” (set to ‘0’) state. To
preserve the battery life when the system is in storage, OSCEN
must be set to ‘1’. This turns off the oscillator circuit, extending
the battery life. If the OSCEN bit goes from disabled to enabled,
it takes approximately one second (two seconds maximum) for
the oscillator to start.
While the system power is off, if the voltage on the backup supply
(VRTCcap or VRTCbat) falls below their respective minimum levels,
the oscillator may fail. The CY14B116K can detect oscillator
failure when system power is restored. This is recorded in the
Oscillator Fail Flag (OSCF) of the Flags register at the address
0x1FFFF0. When the device is powered on (VCC goes above
VSWITCH), the OSCEN bit is checked for the ‘enabled’ status. If
the OSCEN bit is enabled and the oscillator is not active within
the first 5 ms, the OSCF bit is set to ‘1’. The system must check
for this condition and then write ‘0’ to clear the flag.
Note that in addition to setting the OSCF flag bit, the time
registers are reset to the ‘Base Time’, which is the value last
written to the timekeeping registers. The control or calibration
registers and the OSCEN bit are not affected by the ‘oscillator
failed’ condition.
The value of OSCF must be reset to ‘0’ when the time registers
are written for the first time. This initializes the state of this bit,
which may have been set when the system was first powered on.
To reset OSCF, set the write bit ‘W’ (in the Flags register at
0x1FFFF0) to a ‘1’ to enable writes to the Flags register. Write a
‘0’ to the OSCF bit and then reset the write bit to ‘0’ to disable
writes.
Calibrating the Clock
The RTC is driven by a quartz-controlled crystal with a nominal
frequency of 32.768 kHz. The clock accuracy depends on the
quality of the crystal and calibration. The crystals available in the
market typically have an error of +20 ppm to +35 ppm. However,
CY14B116K employs a calibration circuit that improves the
accuracy to +1/–2 ppm at any given temperature. This implies an
error of +2.5 seconds to –5 seconds per month.
The calibration circuit adds or subtracts counts from the oscillator
divider circuit to achieve this accuracy. The number of pulses that
are suppressed (subtracted, negative calibration) or split (added,
positive calibration) depends upon the value loaded into the five
calibration bits found in the Calibration register at 0x1FFFF8.
The calibration bits occupy the five lower order bits in the
Calibration register. These bits are set to represent any value
between ‘0’ and 31 in binary form. Bit D5 is a sign bit, where a
‘1’ indicates positive calibration and a ‘0’ indicates negative
calibration. Adding counts speeds the clock up and subtracting
counts slows the clock down. If a binary ‘1’ is loaded into the
register, it corresponds to an adjustment of 4.068 or –2.034-ppm
offset in oscillator error, depending on the sign.
Calibration occurs within a 64-minute cycle. The first 62 minutes
in the cycle may, once every minute, have one second shortened
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is
loaded into the register, only the first two minutes of the
64-minute cycle are modified. If a binary 6 is loaded, the first 12
are affected, and so on. Therefore, each calibration step has the
effect of adding 512 or subtracting 256 oscillator cycles for every
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm
of adjustment for every calibration step in the Calibration register.
To determine the required calibration, the CAL bit in the Flags
register (0x1FFFF0) must be set to ‘1’. This causes the INT pin
to toggle at a nominal frequency of 512 Hz. Any deviation
measured from 512 Hz indicates the degree and direction of the
required correction. For example, a reading of 512.01024 Hz
indicates a +20-ppm error. Hence, a decimal value of –10
(001010b) must be loaded into the Calibration register to offset
this error.
Note Setting or changing the Calibration register does not affect
the test output frequency.
To set or clear CAL, set the write bit ‘W’ (in the flags register at
0x1FFFF0) to ‘1’ to enable writes to the flags register. Write a
value to CAL, and then reset the write bit to ‘0’ to disable writes.
Alarm
The alarm function compares user-programmed values of alarm
time and date (stored in the registers 0x1FFFF2-0x1FFFF5) with
the corresponding time of day and date values. When a match
occurs, the alarm interrupt flag (AF) is set and an interrupt is
generated on the INT pin if the Alarm Interrupt Enable (AIE) bit
is set.
There are four alarm match fields – date, hours, minutes, and
seconds. Each of these fields has a match bit that is used to
determine if the field is used in the alarm match logic. Setting the
match bit to ‘0’ indicates that the corresponding field is used in
the match process. Depending on the match bits, the alarm
occurs as specifically as once a month or as frequently as once
every minute. Selecting none of the match bits (all 1s) indicates
that no match is required and therefore, the alarm is disabled.
Selecting all match bits (all 0s) causes an exact time and date
match.
There are two ways to detect an alarm event: by reading the AF
flag or monitoring the INT pin. The AF flag in the flags register at
0x1FFFF0 indicates that a date or time match has occurred. The
AF bit is set to ‘1’ when a match occurs. Reading the flags
register clears the alarm flag bit (and all of the register bits). A
hardware interrupt pin may also be used to detect an alarm
event.
Document #: 001-67786 Rev. *J
Page 11 of 42

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