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PDF FM28V202A Data sheet ( Hoja de datos )

Número de pieza FM28V202A
Descripción 2-Mbit (128 K x 16) F-RAM Memory
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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FM28V202A
2-Mbit (128 K × 16) F-RAM Memory
2-Mbit (128 K × 16) F-RAM Memory
Features
2-Mbit ferroelectric random access memory (F-RAM) logically
organized as 128 K × 16
Configurable as 256 K × 8 using UB and LB
High-endurance 100 trillion (1014) read/writes
151-year data retention (see the Data Retention and
Endurance table)
NoDelay™ writes
Page mode operation to 30-ns cycle time
Advanced high-reliability ferroelectric process
SRAM compatible
Industry-standard 128 K × 16 SRAM pinout
60-ns access time, 90-ns cycle time
Advanced features
Software-programmable block write-protect
Superior to battery-backed SRAM modules
No battery concerns
Monolithic reliability
True surface mount solution, no rework steps
Superior for moisture, shock, and vibration
Low power consumption
Active current 7 mA (typ)
Standby current 120 A (typ)
Low-voltage operation: VDD = 2.0 V to 3.6 V
Logic Block Diagram
Industrial temperature: –40 C to +85 C
44-pin thin small outline package (TSOP) Type II
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The FM28V202A is a 128 K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write timing and high
write endurance make the F-RAM superior to other types of
memory.
The FM28V202A operation is similar to that of other RAM
devices and therefore, it can be used as a drop-in replacement
for a standard SRAM in a system. Read cycles may be triggered
by CE or simply by changing the address and write cycles may
be triggered by CE or WE. The F-RAM memory is nonvolatile
due to its unique ferroelectric memory process. These features
make the FM28V202A ideal for nonvolatile memory applications
requiring frequent or rapid writes.
The device is available in a 400-mil, 44-pin TSOP-II surface
mount package. Device specifications are guaranteed over the
industrial temperature range –40 °C to +85 °C.
For a complete list of related documentation, click here.
16 K x 16 block 16 K x 16 block
A16-0
A16-2
A 1-0
CE
WE
UB, LB
OE
ZZ
Control
Logic
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
16 K x 16 block 16 K x 16 block
...
Column Decoder
I/O Latch & Bus Driver
DQ15-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-90309 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 12, 2015

1 page




FM28V202A pdf
FM28V202A
Figure 2. Sleep/Standby State Diagram
Power
Applied
CE HIGH,
ZZ HIGH
Standby
ZZ LOW
Initialize
CE LOW,
ZZ HIGH
CE HIGH,
ZZ HIGH
CE LOW,
ZZ HIGH
Normal
Operation
ZZ LOW
Sleep
ZZ HIGH
Software Write Protect
The 128 K × 16 address space is divided into eight sectors
(blocks) of 16 K × 16 each. Each sector can be individually
software write-protected and the settings are nonvolatile. A
unique address and command sequence invokes the
write-protect mode.
To modify write protection, the system host must issue six read
commands, three write commands, and a final read command.
The specific sequence of read addresses must be provided to
access the write-protect mode. Following the read address
sequence, the host must write a data byte that specifies the
desired protection state of each sector. For confirmation, the
system must then write the complement of the protection byte
immediately after the protection byte. Any error that occurs
including read addresses in the wrong order, issuing a seventh
read address, or failing to complement the protection value will
leave the write protection unchanged.
The write-protect state machine monitors all addresses, taking
no action until this particular read/write sequence occurs. During
the address sequence, each read will occur as a valid operation
and data from the corresponding addresses will be driven to the
data bus. Any address that occurs out of sequence will cause the
software protection state machine to start over. After the address
sequence is completed, the next operation must be a write cycle.
The lower data byte contains the write-protect settings. This
value will not be written to the memory array, so the address is a
don't-care. Rather it will be held pending the next cycle, which
must be a write of the data complement to the protection settings.
If the complement is correct, the write-protect settings will be
adjusted. Otherwise, the process is aborted and the address
sequence starts over. The data value written after the correct six
addresses will not be entered into the memory.
The protection data byte consists of eight bits, each associated
with the write-protect state of a sector. The data byte must be
driven to the lower eight bits of the data bus, DQ7 - DQ0. Setting
a bit to ‘1’ write-protects the corresponding sector; a 0 enables
writes for that sector. The following table shows the write-protect
sectors with the corresponding bit that controls the write-protect
setting.
Table 1. Write Protect Sectors - 16K x 16 Blocks
Sectors
Sector 7
Sector 6
Sector 5
Blocks
1FFFFh–1C000h
1BFFFh–18000h
17FFFh–14000h
Sector 4
Sector 3
Sector 2
Sector 1
Sector 0
13FFFh–10000h
0FFFFh–0C000h
0BFFFh–08000h
07FFFh–04000h
03FFFh–00000h
The write-protect address sequence follows:
1. Read address 12555h
2. Read address 1DAAAh
3. Read address 01333h
4. Read address 0ECCCh
5. Read address 000FFh
6. Read address 1FF00h
7. Write address 1DAAAh
8. Write address 0ECCCh
9. Write address 0FF00h
10.Read address 00000h
The address sequence provides a secure way of modifying the
protection. The write-protect sequence has a one in 3 × 1032
chance of randomly accessing exactly the first six addresses.
The odds are further reduced by requiring three more write
cycles, one that requires an exact inversion of the data byte.
Figure 3 on page 6 shows a flow chart of the entire write-protect
operation. The write-protect settings are nonvolatile. The factory
default: all blocks are unprotected.
For example, the following sequence write-protects addresses
from 0C000h to 13FFFh (sectors 3 and 4):
Read
Read
Read
Read
Read
Read
Write
Write
Write
Read
Address
12555h
1DAAAh
01333h
0ECCCh
000FFh
1FF00h
1DAAAh
0ECCCh
0FF00h
00000h
Data
18h; bits 3 and 4 = 1
E7h; complement of 18h
Don’t care
Document Number: 001-90309 Rev. *F
Page 5 of 22

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FM28V202A arduino
FM28V202A
AC Switching Characteristics
Over the Operating Range
Parameters [3]
Cypress
Alt
Parameter Parameter
Description
SRAM Read Cycle
tCE
tRC
tAA
tOH
tAAP
tOHP
tCA
tPC
tBA
tAS
tAH
tOE
tHZ[4, 5]
tOHZ[4, 5]
tBHZ[4, 5]
tACE
tOHA
tBW
tSA
tHA
tDOE
tHZCE
tHZOE
tHZBE
Chip enable access time
Read cycle time
Address access time, A16-2
Output hold time, A16-2
Page mode access time, A1-0
Page mode output hold time, A1-0
Chip enable active time
Pre-charge time
UB, LB access time
Address setup time (to CE LOW)
Address hold time (CE Controlled)
Output enable access time
Chip Enable to output HI-Z
Output enable HIGH to output HI-Z
UB, LB HIGHHIGH to output HI-Z
VDD = 2.0 V to 2.7 V
Min Max
VDD = 2.7 V to 3.6 V
Min Max
Unit
– 70
105 –
– 105
20 –
– 40
3–
70 –
35 –
– 25
0–
70 –
– 25
– 15
– 15
– 15
90
20
3
60
30
0
60
60 ns
ns
90 ns
– ns
30 ns
– ns
– ns
– ns
15 ns
– ns
– ns
15 ns
10 ns
10 ns
10 ns
Notes
3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified
IOL/IOH and 30-pF load capacitance shown in AC Test Conditions on page 10.
4. tHZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state.
5. This parameter is characterized but not 100% tested.
Document Number: 001-90309 Rev. *F
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