PDF FM28V100 Data sheet ( Hoja de datos )

Número de pieza	FM28V100
Descripción	1-Mbit (128 K x 8) F-RAM Memory
Fabricantes	Cypress Semiconductor
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FM28V100 1-Mbit (128 K × 8) F-RAM Memory 1-Mbit (128 K × 8) F-RAM Memory Features ■ 1-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 8 ❐ High-endurance 100 trillion (1014) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page mode operation to 30 ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 128 K × 8 SRAM pinout ❐ 60-ns access time, 90-ns cycle time ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 7 mA (typ) ❐ Standby current 90 A (typ) ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Industrial temperature: –40 C to +85 C Logic Block Diagram ■ 32-pin thin small outline package (TSOP) Type I ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM28V100 is a 128 K × 8 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM28V100 operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Read and write cycles may be triggered by chip enable or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM28V100 ideal for nonvolatile memory applications requiring frequent or rapid writes. The device is available in a 32-pin TSOP I surface mount package. Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C. For a complete list of related documentation, click here. A16-0 CE 1, CE2 WE OE A 16-3 A 2-0 Control Logic 128 K x 8 F-RAM Array ... Column Decoder I/O Latch & Bus Driver DQ 7-0 Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-86202 Rev. E • San Jose, CA 95134-1709 • 408-943-2600 Revised August 12, 2015 1 page FM28V100 random addresses can be issued is tRC and tWC, respectively. SRAM Drop-In Replacement The FM28V100 is designed to be a drop-in replacement for standard asynchronous SRAMs. The device does not require chip enable pins to toggle for each new address. Both chip enable pins may remain active indefinitely while VDD is applied. When both chip enable pins are active, the device automatically detects address changes and a new access begins. It also allows page mode operation at speeds up to 33 MHz. A typical application is shown in Figure 2. It shows a pull-up resistor on CE1, which will keep the pin HIGH during power cycles, assuming the MCU / MPU pin tristates during the reset condition.The pull-up resistor value should be chosen to ensure the CE1 pin tracks VDD to a high enough value, so that the current drawn when CE1 is LOW is not an issue. Although not required, it is recommended that CE2 be tied to VDD if the controller provides an active-low chip enable. A 10-k resistor draws 330 µA when CE1 is LOW and VDD = 3.3 V. Figure 2. Use of Pull-up Resistor on CE1 VDD FM28V100 MCU / MPU CE2 CE1 WE OE A 16-0 DQ7-0 Note that if CE1 is tied to ground and CE2 tied to VDD, the user must be sure WE is not LOW at power-up or power-down events. If the chip is enabled and WE is LOW during power cycles, data will be corrupted. Figure 3 shows a pull-up resistor on WE, which will keep the pin HIGH during power cycles, assuming the MCU/MPU pin tristates during the reset condition.The pull-up resistor value should be chosen to ensure the WE pin tracks VDD to a high enough value, so that the current drawn when WE is LOW is not an issue. A 10-k resistor draws 330 µA when WE is LOW and VDD = 3.3 V. Figure 3. Use of Pull-up Resistor on WE VDD FM28V100 CE2 CE1 MCU / MPU WE OE A16-0 DQ7-0 For applications that require the lowest power consumption, the chip enable signal should be active only during memory accesses. Due to the external pull-up resistor, some supply current will be drawn while CE1 is LOW. When CE1 is HIGH, the device draws no more than the maximum standby current ISB. Document Number: 001-86202 Rev. E Page 5 of 18 5 Page CE1 CE2 A16-0 WE DQ 7-0 Figure 7. Write Cycle Timing 1 (WE Controlled) [11] tCA tCW tPC tAS tWLC tWZ D out tWP tDH ttDDSS D in tWX tHZ D out A16-0 WE DQ 7-0 CE1 Figure 8. Write Cycle Timing 2 (CE Controlled) tCA tPC CE2 A16-0 WE DQ 7-0 tAS tWS tAH tWH tDS D in tDH Figure 9. Write Cycle Timing 3 (CE1 LOW, CE2 HIGH) [11] tWC tAWH D out tWLA tWX tWZ tDH tDS D in D out D in Note 11. OE (not shown) is LOW only to show the effect of WE on DQ pins. Document Number: 001-86202 Rev. *E FM28V100 Page 11 of 18 11 Page

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