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PDF S29VS064R Data sheet ( Hoja de datos )

Número de pieza S29VS064R
Descripción 64 Mbit (4M x 16-bit) Flash
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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No Preview Available ! S29VS064R Hoja de datos, Descripción, Manual

S29VS064R
S29XS064R
64 Mbit (4M x 16-bit), 1.8 V, Multiplexed,
Burst, MirrorBit® Flash
Distinctive Characteristics
Single 1.8 volt read, program and erase
(1.7 to 1.95 volt)
VersatileIO™ Feature
– Device generates data output voltages and tolerates data input
voltages as determined by the voltage on the VCCQ pin
– 1.8 V compatible I/O signals
Address and Data Interface Options
– Address and Data Multiplexed for reduced I/O count
(ADM) S29VS-R
– Address-High, Address-Low, Data Multiplexed for minimum I/O
count (AADM) S29XS-R
Simultaneous Read/Write operation
– Data can be continuously read from one bank while executing
erase/program functions in other bank
– Zero latency between read and write operations
Burst length
– Continuous linear burst
– 8/16 word linear burst with wrap around
Secured Silicon Sector region
– 256 words accessible through a command sequence, 128 words
for the Factory Secured Silicon Sector and 128 words for the
Customer Secured Silicon Sector.
Sector Architecture
– Four 8 kword sectors in upper-most address range
– One hundred twenty-seven 32 kword sectors
– Four banks
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch. Latency, ns (tIACC)
Max. Synch. Burst Access, ns (tBACC)
Max. Asynch. Access Time, ns (tACC)
Max OE# Access Time, ns (tOE)
108
80
7.6
80
15
Security Features
Dynamic Protection Bit (DYB)
– A command sector protection method to lock combinations of
individual sectors to prevent program or erase operations within
that sector
– Sectors can be locked and unlocked in-system at VCC level
Hardware Sector Protection
– All sectors locked when VPP = VIL
Handshaking feature
– Provides host system with minimum possible latency by
monitoring RDY
Supports Common Flash Memory
Interface (CFI)
Manufactured on 65 nm MirrorBit® process technology
Cycling endurance: 100,000 cycles per sector typical
Data retention: 10 years typical
Data# Polling and toggle bits
– Provides a software method of detecting program and erase
operation completion
Erase Suspend/Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Program Suspend/Resume
– Suspends a programming operation to read data from a sector
other than the one being programmed, then resume the
programming operation
Packages
– 44-ball Very Thin FBGA
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VPP) Per Word
Sector Erase (8 kword Sector)
Sector Erase (32 kword Sector)
170 µs
14.1 µs
9 µs
350 ms
800 ms
Current Consumption (typical values)
Continuous Burst Read @ 108 MHz
Simultaneous Operation @ 108 MHz
Program/Erase
Standby Mode
32 mA
71 mA
30 mA
20 µA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00949 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 17, 2015

1 page




S29VS064R pdf
S29VS064R
S29XS064R
2. Block Diagrams
VCCQ
VCC
VSS
WE#
RESET#
VPP
CE#
OE#
RDY
Buffer
State
Control
Command
Register
RDY
Erase Voltage
Generator
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
A/DQ15–A/DQ0
Input/Output
Buffers
Data
Latch
VCC
Detector
AVD#
CLK
Burst
State
Control
A/DQ15–A/DQ0
Amax–A16
Timer
Burst
Address
Counter
Amax–A0
Note:
Amax indicates the highest order address bit. Amax equals A21 for S29VS/XS064R.
Y-Decoder
X-Decoder
Y-Gating
Cell Matrix
Document Number: 002-00949 Rev. *G
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S29VS064R arduino
S29VS064R
S29XS064R
8. Address/Data Configuration (Interface) Modes
There are two options for connection to the address and data buses.
Address and Data Multiplexed (ADM) mode - On the S29VS-R devices upper address is supplied on separate signal inputs and
the lower 16-bits of address are multiplexed with 16-bit data on the A/DQ15 to A/DQ0 I/Os.
Address-high, Address-low, and Data Multiplexed (AADM) mode - On the S29XS-R devices upper and lower address are
multiplexed with 16-bit data on the A/DQ15 to A/D0 signal I/Os.
The two options allow use with the traditional address/data multiplexed NOR interface (S29VS family), or an address multiplexed/
data multiplexed interface with the lowest signal count (S29XS family).
ADM or AADM mode can be selected via ordering part number only.
8.1 ADM Interface Mode (S29VS064R)
In ADM mode, the AVD# signal is used to capture the entire address with a single toggle of AVD# in asynchronous mode or in a
single clock cycle in synchronous mode.
8.2 AADM Interface Mode (S29XS064R)
Signal input and output (I/O) connections on a high complexity component such as an Application Specific Integrated Circuit (ASIC)
are a limited resource. Reducing signal count on any interface of the ASIC allows for either more features or lower package cost.
The memory interface described in this section is intended to reduce the I/O signal count associated with the flash memory interface
with an ASIC.
The interface is called Address-High, Address-Low, and Data Multiplexed (AADM) because all address and data information is time
multiplexed on a single 16-bit wide bus. This interface is electrically compatible with existing ADM 16-bit wide random access static
memory interfaces but uses fewer address signals. In that sense AADM is a signal count subset of existing static memory interfaces.
This interface can be implemented in existing memory controller designs, as an additional mode, with minimal changes. No new
I/O technology is needed and existing memory interfaces can continue to be supported while the electronics industry adopts this
new interface. ASIC designers can reuse the existing memory address signals above A15 for other functions when an AADM
memory is in use.
By breaking up the memory address in to two time slots the address is naturally extended to be a 32-bit word address. But, using
two bus cycles to transfer the address increases initial access latency by increasing the time address is using the bus. However,
many memory accesses are to locations in memory nearby the previous access. Very often it is not necessary to provide both cycles
of address. This interface stores the high half of address in the memory so that if the high half of address does not change from the
previous access, only the low half of address needs to be sent on the bus. If a new upper address is not captured at the beginning of
an access the last captured value of the upper address is used. This allows accesses within the same 128-kbyte address range to
provide only the lower address as part of each access.
In AADM mode two signal rising edges are needed to capture the upper and lower address portions in asynchronous mode or two
signal combinations over two clocks is needed in synchronous mode. In asynchronous mode the upper address is captured by an
AVD# rising edge when OE# is Low; the lower address is captured on the rising edge of AVD# with OE# High. In synchronous mode
the upper address is captured at the rising clock edge when AVD# and OE# are Low; the lower address is captured at the rising
edge of clock when AVD# is Low and OE# is High.
CE# going High at any time during the access or OE# returning High after RDY is first asserted High during an access, terminates
the read access and causes the address/data bus direction to switch back to input mode. The address/data bus direction switches
from input to output mode only after an Address-Low capture when AVD# is Low and OE# is High. This prevents the assertion of
OE# during Address-High capture from causing a bus conflict between the host address and memory data signals. Note, in burst
mode, this implies at least one cycle of CE# or OE# High before an Address-high for a new access may be placed on the bus so that
there is time for the memory to recognize the end of the previous access, stop driving data outputs, and ignore OE# so that assertion
of OE# with the new Address-high does not create a bus conflict with a new address being driven on the bus. At high bus
frequencies more than one cycle may be need in order to allow time for data outputs to stop driving and new address to be driven
(bus turn around time).
During a write access, the address/data bus direction is always in the input mode.
Document Number: 002-00949 Rev. *G
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