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PDF S29GL128S Data sheet ( Hoja de datos )

Número de pieza S29GL128S
Descripción 3.0V GL-S Flash Memory
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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S29GL01GS, S29GL512S
S29GL256S, S29GL128S
1 Gbit (128 Mbyte), 512 Mbit (64 Mbyte),
256 Mbit (32 Mbyte), 128 Mbit (16 Mbyte),
3.0V GL-S Flash Memory
General Description
The Cypress® S29GL01G/512/256/128S are MirrorBit® Eclipse flash products fabricated on 65 nm process technology. These
devices offer a fast page access time as fast as 15 ns with a corresponding random access time as fast as 90 ns. They feature a
Write Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective
programming time than standard programming algorithms. This makes these devices ideal for today’s embedded applications that
require higher density, better performance and lower power consumption.
Distinctive Characteristics
CMOS 3.0 Volt Core with Versatile I/O
65 nm MirrorBit Eclipse Technology
Single supply (VCC) for read / program / erase (2.7V to 3.6V)
Versatile I/O Feature
– Wide I/O voltage range (VIO): 1.65V to VCC
x16 data bus
Asynchronous 32-byte Page read
512-byte Programming Buffer
– Programming in Page multiples, up to a maximum of 512
bytes
Single word and multiple program on same word options
Automatic Error Checking and Correction (ECC) – internal
hardware ECC with single bit error correction
Sector Erase
– Uniform 128-kbyte sectors
Suspend and Resume commands for Program and Erase
operations
Status Register, Data Polling, and Ready/Busy pin methods
to determine device status
Advanced Sector Protection (ASP)
– Volatile and non-volatile protection methods for each
sector
Separate 1024-byte One Time Program (OTP) array with two
lockable regions
Common Flash Interface (CFI) parameter table
Temperature Range / Grade
– Industrial (-40°C to +85°C)
– Industrial Plus(-40°C to +105°C)
– Automotive, AEC-Q100 Grade 3 (-40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (-40 °C to +105 °C)
100,000 Program / Erase Cycles
20 Years Data Retention
Packaging Options
– 56-pin TSOP
– 64-ball LAA Fortified BGA, 13 mm x 11 mm
– 64-ball LAE Fortified BGA, 9 mm x 9 mm
– 56-ball VBU Fortified BGA, 9 mm x 7 mm
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98285 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 10, 2016

1 page




S29GL128S pdf
S29GL01GS, S29GL512S
S29GL256S, S29GL128S
Table 1.1 S29GL-S Address Map
Type
Address within Page
Address within Write Buffer
Page
Write-Buffer-Line
Sector
Count
16
256
4096
256
1024 (1 Gb)
512 (512 Mb)
256 (256 Mb)
128 (128 Mb)
Addresses
A3 - A0
A7 - A0
A15 - A4
A15 - A8
AMAX - A16
The device control logic is subdivided into two parallel operating sections, the Host Interface Controller (HIC) and the Embedded
Algorithm Controller (EAC). HIC monitors signal levels on the device inputs and drives outputs as needed to complete read and write
data transfers with the host system. HIC delivers data from the currently entered address map on read transfers; places write
transfer address and data information into the EAC command memory; notifies the EAC of power transition, hardware reset, and
write transfers. The EAC looks in the command memory, after a write transfer, for legal command sequences and performs the
related Embedded Algorithms.
Changing the non-volatile data in the memory array requires a complex sequence of operations that are called Embedded
Algorithms (EA). The algorithms are managed entirely by the device internal EAC. The main algorithms perform programming and
erase of the main array data. The host system writes command codes to the flash device address space. The EAC receives the
commands, performs all the necessary steps to complete the command, and provides status information during the progress of an
EA.
The erased state of each memory bit is a logic 1. Programming changes a logic 1 (High) to a logic 0 (Low). Only an Erase operation
is able to change a 0 to a 1. An erase operation must be performed on an entire 128-kbyte aligned and length group of data call a
Sector. When shipped from Cypress all Sectors are erased.
Programming is done via a 512-byte Write Buffer. It is possible to write from 1 to 256 words, anywhere within the Write Buffer before
starting a programming operation. Within the flash memory array, each 512-byte aligned group of 512 bytes is called a Line. A
programming operation transfers volatile data from the Write Buffer to a non-volatile memory array Line. The operation is called
Write Buffer Programming.
As the device transfers each 32-byte aligned page of data that was loaded into the Write buffer to the 512-byte Flash array line,
internal logic programs an ECC Code for the Page into a portion of the memory array not visible to the host system software. The
internal logic checks the ECC information during the initial access of every array read operation. If needed, the ECC information
corrects a one bit error during the initial access time.
The Write Buffer is filled with 1’s after reset or the completion of any operation using the Write Buffer. Any locations not written to a 0
by a Write to Buffer command are by default still filled with 1’s. Any 1’s in the Write Buffer do not affect data in the memory array
during a programming operation.
As each Page of data that was loaded into the Write Buffer is transferred to a memory array Line.
Sectors may be individually protected from program and erase operations by the Advanced Sector Protection (ASP) feature set.
ASP provides several, hardware and software controlled, volatile and non-volatile, methods to select which sectors are protected
from program and erase operations.
Document Number: 001-98285 Rev. *K
Page 5 of 107

5 Page





S29GL128S arduino
S29GL01GS, S29GL512S
S29GL256S, S29GL128S
2.7 Sector Protection Control
2.7.1
Lock Register ASO
The Lock register ASO contains a single word of OTP memory. When the ASO is entered the Lock Register appears at all word
locations in the device address space. See Figure 11.16, ASO Entry Timing on page 87 for ASO Entry timing requirements.
However, it is recommended to read or program the Lock Register only at location 0 of the device address space for future
compatibility.
2.7.2
Persistent Protection Bits (PPB) ASO
The PPB ASO contains one bit of a Flash Memory Array for each Sector in the device. When the PPB ASO is entered, the PPB bit
for a sector appears in the Least Significant Bit (LSB) of each address in the sector. See Figure 11.16, ASO Entry Timing
on page 87 for ASO Entry timing requirements. Reading any address in a sector displays data where the LSB indicates the non-
volatile protection status for that sector. However, it is recommended to read or program the PPB only at address 0 of the sector for
future compatibility. If the bit is 0 the sector is protected against programming and erase operations. If the bit is 1 the sector is not
protected by the PPB. The sector may be protected by other features of ASP.
2.7.3
PPB LOCK ASO
The PPB Lock ASO contains a single bit of volatile memory. The bit controls whether the bits in the PPB ASO may be programmed
or erased. If the bit is 0 the PPB ASO is protected against programming and erase operations. If the bit is 1 the PPB ASO is not
protected. When the PPB Lock ASO is entered the PPB Lock bit appears in the Least Significant Bit (LSB) of each address in the
device address space. See Figure 11.16, ASO Entry Timing on page 87 for ASO Entry timing requirements. However, it is
recommended to read or program the PPB Lock only at address 0 of the device for future compatibility.
2.7.4
Password ASO
The Password ASO contains four words of OTP memory. When the ASO is entered the Password appears starting at address 0 in
the device address space. See Figure 11.16, ASO Entry Timing on page 87 for ASO Entry timing requirements. All locations above
the forth word are undefined.
2.7.5
Dynamic Protection Bits (DYB) ASO
The DYB ASO contains one bit of a volatile memory array for each Sector in the device. When the DYB ASO is entered, the DYB bit
for a sector appears in the Least Significant Bit (LSB) of each address in the sector. See Figure 11.16, ASO Entry Timing
on page 87 for ASO Entry timing requirements. Reading any address in a sector displays data where the LSB indicates the non-
volatile protection status for that sector. However, it is recommended to read, set, or clear the DYB only at address 0 of the sector for
future compatibility. If the bit is 0 the sector is protected against programming and erase operations. If the bit is 1 the sector is not
protected by the DYB. The sector may be protected by other features of ASP.
2.8 ECC Status ASO
The system can access the ECC Status ASO by issuing the ECC Status entry command sequence during Read Mode. The ECC
Status ASO provides the enabled or disabled status of the ECC function or if the ECC function corrected a Single Bit Error when
reading the selected Page. Section 5.3, Automatic ECC on page 22 describes the ECC function in more detail. See Figure 11.16,
ASO Entry Timing on page 87 for ASO Entry timing requirements.
The ECC Status ASO allows the following activities:
Read ECC Status for the selected page.
ASO Exit.
2.8.1 ECC Status
The contents of the ECC Status ASO indicates, for the selected ECC page, whether ECC protection has corrected an error in the
ECC page eight-bit error correction code, the ECC page of 16 Words of data, or that ECC is disabled for that ECC unit. The address
specified in the ECC Status Read Command, provided in Table 7.1 on page 55 selects the ECC Page.
Document Number: 001-98285 Rev. *K
Page 11 of 107

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