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PDF S29AL016J Data sheet ( Hoja de datos )
| Número de pieza | S29AL016J | |
| Descripción | Boot Sector Flash | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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S29AL016J
Distinctive Characteristics
16 Mbit (2 M x 8-Bit/1 M x 16-Bit), 3 V
Boot Sector Flash
Architectural Advantages
Single Power Supply Operation
– Full voltage range: 2.7 to 3.6 volt read and write operations for
battery-powered applications
Manufactured on 110 nm Process Technology
– Fully compatible with 200 nm S29AL016D
Secured Silicon Sector region
– 128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
accessible through a command sequence
– May be programmed and locked at the factory or by the customer
Flexible Sector Architecture
– One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte
sectors (byte mode)
– One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32
Kword sectors (word mode)
Sector Group Protection Features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
Performance Characteristics
High Performance
– Access times as fast as 55 ns
– Extended temperature range (–40°C to +125°C)
Ultra Low Power Consumption (typical values at 5 MHz)
– 0.2 µA Automatic Sleep mode current
– 0.2 µA standby mode current
– 7 mA read current
– 20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Package Options
48-ball Fine-pitch BGA
64-ball Fortified BGA
48-pin TSOP
Software Features
CFI (Common Flash Interface) Compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Data# Polling and Toggle Bits
– Provides a software method of detecting program or erase
operation completion
Hardware Features
Ready/Busy# Pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
– Hardware method to reset the device to reading array data
WP# input pin
– For boot sector devices: at VIL, protects first or last 16 Kbyte
sector depending on boot configuration (top boot or bottom boot)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-00777 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 08, 2015
1 page  
3. Connection Diagrams
Figure 3.1 48-pin Standard TSOP (TS048)
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
S29AL016J
48 A16
47 BYTE#
46 VSS
45 DQ15/A-1
44 DQ7
43 DQ14
42 DQ6
41 DQ13
40 DQ5
39 DQ12
38 DQ4
37 VCC
36 DQ11
35 DQ3
34 DQ10
33 DQ2
32 DQ9
31 DQ1
30 DQ8
29 DQ0
28 OE#
27 VSS
26 CE#
25 A0
Document Number: 002-00777 Rev. *L
Page 5 of 58
5 Page 
S29AL016J
S29AL016J Device Bus Operations
Operation
Reset
CE# OE# WE# RESET#
X XX
L
WP#
X
Sector Group Protect
(2) (3)
L
HL
VID
H
Sector Group
Unprotect (2) (3)
Temporary Sector
Group Unprotect
L HL
VID
X XX
VID
H
H
Addresses
(Note 1)
X
Sector Address,
A6 = L,
A3 = A2 = L,
A1 = H, A0 = L
Sector Address,
A6 = H,
A3 = A2 = L,
A1 = H, A0 = L
AIN
DQ0–
DQ7
High-Z
BYTE#
= VIH
High-Z
DQ8–DQ15
BYTE#
= VIL
High-Z
(Note 4)
X
X
(Note 4)
X
(Note 4) (Note 4)
X
High-Z
Legend
L = Logic Low = VIL; H = Logic High = VIH; VID = 8.5 V to 12.5 V; X = Don’t Care; AIN = Address In; DOUT = Data Out
Notes
1. Address In = Amax:A0 in WORD mode (BYTE#=VIH), Address In = Amax:A-1 in BYTE mode (BYTE#=VIL). Sector addresses are Amax to A12 in both WORD mode
and BYTE mode.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See Section 7.10, Sector Group Protection/Unprotection
on page 16.
3. If WP# = VIL, the outermost sector remains protected (determined by device configuration). If WP# = VIH, the outermost sector protection depends on whether the
sector was last protected or unprotected using the method described in Section 7.10, Sector Group Protection/Unprotection on page 16. The WP# contains an internal
pull-up; when unconnected, WP is at VIH.
4. DIN or DOUT as required by command sequence, data polling, or sector group protection algorithm.
7.1 Word/Byte Configuration
The BYTE# pin controls whether the device data I/O pins DQ15–DQ0 operate in the byte or word configuration. If the BYTE# pin is
set at logic 1, the device is in word configuration, DQ15–DQ0 are active and controlled by CE# and OE#.
If the BYTE# pin is set at logic 0, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by
CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function.
7.2 Requirements for Reading Array Data
To read array data from the outputs, the system must drive the CE# and OE# pins to VIL. CE# is the power control and selects the
device. OE# is the output control and gates array data to the output pins. WE# should remain at VIH. The BYTE# pin determines
whether the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the
device data outputs. The device remains enabled for read access until the command register contents are altered.
See Reading Array Data on page 24 for more information. Refer to the AC Read Operations on page 39 for timing specifications and
to Figure 17.1 on page 39 for the timing diagram. ICC1 in DC Characteristics on page 37 represents the active current specification
for reading array data.
7.3 Writing Commands/Command Sequences
To write a command or command sequence (which includes programming data to the device and erasing sectors of memory), the
system must drive WE# and CE# to VIL, and OE# to VIH.
For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. See Word/Byte
Configuration on page 11 for more information.
Document Number: 002-00777 Rev. *L
Page 11 of 58
11 Page | ||
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