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PDF S70FL01GS Data sheet ( Hoja de datos )
| Número de pieza | S70FL01GS | |
| Descripción | 1 Gbit (128 Mbyte) 3.0V SPI Flash | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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S70FL01GS
1 Gbit (128 Mbyte) 3.0V SPI Flash
Features
CMOS 3.0V Core
Serial Peripheral Interface (SPI) with Multi-I/O
– SPI Clock polarity and phase modes 0 and 3
– Double Data Rate (DDR) option
– Extended Addressing: 32-bit address
– Serial Command set and footprint compatible with
S25FL-A, S25FL-K, and S25FL-P SPI families
– Multi I/O Command set and footprint compatible with
S25FL-P SPI family
READ Commands
– Normal, Fast, Dual, Quad, Fast DDR, Dual DDR, Quad
DDR
– AutoBoot – power up or reset and execute a Normal or
Quad read command automatically at a preselected
address
– Common Flash Interface (CFI) data for configuration
information
Programming (1.5 Mbytes/s)
– 512-byte Page Programming buffer
– Quad-Input Page Programming (QPP) for slow clock
systems
– Automatic Error Correction Code (ECC): Internal hardware
ECC generation with single bit error correction
Erase (0.5 Mbytes/s)
– Uniform 256-kbyte sectors
Cycling Endurance
– 100,000 Program-Erase Cycles, minimum
Data Retention
– 20 Year Data Retention, minimum
Security Features
One Time Program (OTP) array of 1024 bytes
Block Protection
– Status Register bits to control protection against program
or erase of a contiguous range of sectors.
– Hardware and software control options
– Advanced Sector Protection (ASP)
– Individual sector protection controlled by boot code or
password
Cypress® 65-nm MirrorBit® Technology with Eclipse
Architecture
Core Supply Voltage: 2.7V to 3.6V
I/O Supply Voltage: 1.65V to 3.6V
Temperature Range / Grade:
– Industrial (40 °C to +85 °C)
– Industrial Plus (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 3 (40 °C to +85 °C)
– Automotive, AEC-Q100 Grade 2 (40 °C to +105 °C)
– Automotive, AEC-Q100 Grade 1 (40 °C to +125 °C)
Packages (all Pb-free)
– 16-lead SOIC (300 mils)
– BGA-24, 8 6 mm
– 5 5 ball (ZSA024) footprint
General Description
This document contains information for the S70FL01GS device, which is a dual die stack of two S25FL512S die. For detailed
specifications, refer to the discrete die datasheet provided in the Affected Documents/Related Documents table.
Affected Documents/Related Documents
Document Title
S25FL512S 512 Mbit (64 Mbyte) 3.0V SPI Flash Memory Datasheet
Publication Number
001-98284
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-98295 Rev. *K
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 08, 2017
1 page  
S70FL01GS
3. Input/Output Summary
Table 1. Signal List
Signal Name
Type
RESET#
Input
SCK
CS#
CS1#
CS2#
SI / IO0
SO / IO1
WP# / IO2
Input
Input
Input
Input
I/O
I/O
I/O
HOLD# / IO3
VCC
VIO
VSS
NC
I/O
Supply
Supply
Supply
Unused
RFU
Reserved
DNU
Reserved
Description
Hardware Reset: Low = device resets and returns to standby state, ready to receive a
command. The signal has an internal pull-up resistor and may be left unconnected in the host
system if not used.
Serial Clock
Chip Select
Chip Select. FL512S #1.
Chip Select. FL512S #2.
Serial Input for single bit data commands or IO0 for Dual or Quad commands.
Serial Output for single bit data commands. IO1 for Dual or Quad commands.
Write Protect when not in Quad mode. IO2 in Quad mode. The signal has an internal pull-up
resistor and may be left unconnected in the host system if not used for Quad commands.
Hold (pause) serial transfer in single bit or Dual data commands. IO3 in Quad-I/O mode. The
signal has an internal pull-up resistor and may be left unconnected in the host system if not used
for Quad commands.
Core Power Supply
Versatile I/O Power Supply. Note: VIO is not supported in the S70FL01GS device. Refer to
Section 7. for more details.
Ground
Not Connected. No device internal signal is connected to the package connector nor is there
any future plan to use the connector for a signal. The connection may safely be used for routing
space for a signal on a Printed Circuit Board (PCB). However, any signal connected to an NC
must not have voltage levels higher than VCC.
Reserved for Future Use. No device internal signal is currently connected to the package
connector but there is potential future use of the connector for a signal. It is recommended to not
use RFU connectors for PCB routing channels so that the PCB may take advantage of future
enhanced features in compatible footprint devices.
Do Not Use. A device internal signal may be connected to the package connector. The
connection may be used by Cypress for test or other purposes and is not intended for connection
to any host system signal. Any DNU signal related function will be inactive when the signal is at
VIL. The signal has an internal pull-down resistor and may be left unconnected in the host system
or may be tied to VSS. Do not use these connections for PCB signal routing channels. Do not
connect any host system signal to this connection.
Document Number: 001-98295 Rev. *K
Page 5 of 18
5 Page 
S70FL01GS
10.1 DDR AC Characteristics
Table 6. DDR AC Characteristics 66 MHz and 80 MHz Operation
Symbol
FSCK, R
PSCK, R
tWH, tCH
tWL, tCL
tCS
tCSS
tCSH
tSU
tHD
tV
tHO
tDIS
tLZ
tIO_skew
Parameter
SCK Clock Frequency for DDR
READ instruction
SCK Clock Period for DDR
READ instruction
Clock High Time
Clock Low Time
CS# High Time (Read
Instructions)
CS# Active Setup Time (relative
to SCK)
CS# Active Hold Time (relative
to SCK)
IO in Setup Time
IO in Hold Time
Clock Low to Output Valid
Output Hold Time
Output Disable Time
Clock to Output Low
Impedance
First IO to last IO data valid
time
66 MHz
Min Typ Max
DC 66
15
45% PSCK
45% PSCK
10
3
3
2 3000 (2)
2
0 6.5 (1)
1.5
8
08
600
Notes:
1. Regulated VCC range (3.0 - 3.6V) and CL =15 pF.
2. Maximum value only applies during Program/Erase Suspend/Resume commands.
Min
DC
12.5
45% PSCK
45% PSCK
10
3
3
1.5
1.5
1.5
0
80 MHz
Typ
Unit
Max
80 MHz
ns
ns
ns
ns
ns
3000 (2)
6.5 (1)
8
8
ns
ns
ns
ns
ns
ns
ns
600 ps
10.2 Capacitance Characteristics
Table 7. Capacitance
CIN
COUT
Parameter
Input Capacitance (applies to SCK, CS#1, CS#2, RESET#)
Output Capacitance (applies to All I/O)
Test Conditions
1 MHz
1 MHz
Note:
1. For more information on capacitance, please consult the IBIS models.
Min
Max
16
16
Unit
pF
pF
Document Number: 001-98295 Rev. *K
Page 11 of 18
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