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PDF S29WS256P Data sheet ( Hoja de datos )

Número de pieza S29WS256P
Descripción Simultaneous Read/Write Flash
Fabricantes Cypress Semiconductor 
Logotipo Cypress Semiconductor Logotipo



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S29WS512P
S29WS256P
S29WS128P
512/256/128 Mb (32/16/8 M x 16 bit), 1.8 V,
Simultaneous Read/Write Flash
Features
Single 1.8 V read/program/erase (1.70–1.95 V)
90 nm MirrorBit™ Technology
Simultaneous Read/Write operation with zero latency
Random page read access mode of 8 words with 20 ns intra page
access time
32 Word / 64 Byte Write Buffer
Sixteen-bank architecture consisting of
32/16/8 Mwords for 512/256/128P, respectively
Four 16 Kword sectors at both top and bottom of memory array
510/254/126 64Kword sectors (WS512/256/128P)
Programmable linear (8/16/32) with or without wrap around and
continuous burst read modes
Secured Silicon Sector region consisting of 128 words each for
factory and 128 words for customer
20-year data retention (typical)
Cycling Endurance: 100,000 cycles per sector (typical)
Command set compatible with JEDEC (42.4) standard
Hardware (WP#) protection of top and bottom sectors
Dual boot sector configuration (top and bottom)
Handshaking by monitoring RDY
Offered Packages
– WS512P/WS256P/WS128P: 84-ball FBGA
(11.6 mm x 8 mm)
Low VCC write inhibit
Persistent and Password methods of Advanced Sector Protection
Write operation status bits indicate program and erase operation
completion
Suspend and Resume commands for Program and Erase
operations
Unlock Bypass program command to reduce programming time
Synchronous or Asynchronous program operation, independent of
burst control register settings
ACC input pin to reduce factory programming time
Support for Common Flash Interface (CFI)
General Description
The Spansion S29WS512/256/128P are Mirrorbit® Flash products fabricated on 90 nm process technology. These burst mode
Flash devices are capable of performing simultaneous read and write operations with zero latency on two separate banks using
separate data and address pins. These products can operate up to 104 MHz and use a single VCC of 1.7 V to 1.95 V that makes
them ideal for today’s demanding wireless applications requiring higher density, better performance and lowered power
consumption.
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max. Synch Access Time (tIACC)
Max. Synch. Burst Access, ns (tBACC)
Max OE# Access Time, ns (tOE)
Max. Asynch. Access Time, ns (tACC)
104
103.8
7.6
7.6
80
Current Consumption (typical values)
Continuous Burst Read @ 104 MHz
Simultaneous Operation 104 MHz
Program
Standby Mode
Typical Program & Erase Times
Single Word Programming
Effective Write Buffer Programming (VCC) Per Word
Effective Write Buffer Programming (VACC) Per Word
Sector Erase (16 Kword Sector)
Sector Erase (64 Kword Sector)
36 mA
40 mA
20 mA
20 µA
40 µs
9.4 µs
6 µs
350 ms
600 ms
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-01747 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 17, 2015

1 page




S29WS256P pdf
3. Block Diagrams
VCC
VSS
VCCQ
AMAX–A0
Bank Address
Bank 0
X-Decoder
WP#
ACC
RESET#
WE#
CEx#
AVD#
RDY
DQ15–DQ0
Bank Address
Bank 1
AMAX–A0
STATE
CONTROL
&
COMMAND
REGISTER
AMAX–A0
X-Decoder
Status
Control
X-Decoder
AMAX–A0
Bank Address
Bank (n-1)
S29WS512P
S29WS256P
S29WS128P
DQ15–DQ0
OE#
DQ15–DQ0
DQ15–DQ0
DQ15–DQ0
Bank Address
X-Decoder
Bank (n)
DQ15–DQ0
Notes:
1. AMAX-A0 = A24-A0 for the WS512P, A23-A0 for the WS256P, and A22-A0 for the WS128P.
2. n = 15 for WS512P / WS256P / WS128P.
4. Physical Dimensions/Connection Diagrams
This section shows the I/O designations and package specifications for the S29WS-P.
4.1 Related Documents
The following documents contain information relating to the S29WS-P devices. Click on the title or go to www.spansion.com to
download the PDF file, or request a copy from your sales office.
Considerations for X-ray Inspection of Surface-Mounted Flash Integrated Circuits
4.2 Special Handling Instructions for FBGA Package
Special handling is required for Flash Memory products in FBGA packages.
Document Number: 002-01747 Rev. *A
Page 5 of 86

5 Page





S29WS256P arduino
S29WS512P
S29WS256P
S29WS128P
S29WS128P Sector & Memory Address Map
Bank Sector Sector
Sector/
Size Count Size (KB) Bank Sector Range
Address Range
Notes
1 MB
4
32
32
32 0
32
SA000
SA001
SA002
SA003
000000h–003FFFh
004000h–007FFFh
008000h–00BFFFh
00C000h–00FFFFh
Contains four smaller
sectors at bottom of
addressable memory.
7 128
SA004 to SA010 010000h–01FFFFh to 070000h–07FFFFh
1 MB
8
128 1 SA011 to SA018 080000h–08FFFFh to 0F0000h–0FFFFFh
1 MB
8
128 2 SA019 to SA026 100000h–10FFFFh to 170000h–17FFFFh
1 MB
8
128 3 SA027 to SA034 180000h–18FFFFh to 1F0000h–1FFFFFh
1 MB
8
128 4 SA035 to SA042 200000h–20FFFFh to 270000h–27FFFFh
1 MB
8
128 5 SA043 to SA050 280000h–28FFFFh to 2F0000h–2FFFFFh
1 MB
1 MB
1 MB
1 MB
8
8
8
8
128 6 SA051 to SA058 300000h–30FFFFh to 370000h–37FFFFh
All 128 KB sectors.
128 7 SA059 to SA066 380000h–38FFFFh to 3F0000h–3FFFFFh Pattern for sector address
128 8 SA067 to SA074 400000h–40FFFFh to 470000h–47FFFFh range is xx0000h–xxFFFFh.
(see note)
128 9 SA075 to SA082 480000h–48FFFFh to 4F0000h–4FFFFFh
1 MB
8
128 10 SA083 to SA090 500000h–50FFFFh to 570000h–57FFFFh
1 MB
8
128 11 SA091 to SA098 580000h–58FFFFh to 5F0000h–5FFFFFh
1 MB
8
128 12 SA099 to SA106 600000h–60FFFFh to 670000h–67FFFFh
1 MB
8
128 13 SA107 to SA114 680000h–68FFFFh to 6F0000h–6FFFFFh
1 MB
8
128 14 SA115 to SA122 700000h–70FFFFh to 770000h–77FFFFh
7 128
SA123 to SA129 780000h–78FFFFh to 7E0000h–7EFFFFh
1 MB
4
32
32 15
32
32
SA130
SA131
SA132
SA133
7F0000h–7F3FFFh
7F4000h–7F7FFFh
7F8000h–7FBFFFh
7FC000h–7FFFFFh
Contains four smaller
sectors at top of
addressable memory.
Note:
This table has been condensed to show sector-related information for an entire device on a single page. Sectors and their address ranges that are not explicitly listed
(such as SA005–SA009) have sector starting and ending addresses that form the same pattern as all other sectors of that size. For example, all 128 KB sectors have the
pattern xx00000h–xxFFFFh.
7. Device Operations
This section describes the read, program, erase, simultaneous read/write operations, handshaking, and reset features of the Flash
devices.
Operations are initiated by writing specific commands or a sequence with specific address and data patterns into the command
registers (see Table on page 75 and Table on page 77). The command register itself does not occupy any addressable memory
location; rather, it is composed of latches that store the commands, along with the address and data information needed to execute
the command. The contents of the register serve as input to the internal state machine and the state machine outputs dictate the
function of the device. Writing incorrect address and data values or writing them in an improper sequence may place the device in an
unknown state, in which case the system must write the reset command to return the device to the reading array data mode.
Document Number: 002-01747 Rev. *A
Page 11 of 86

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