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PDF ZSSC1956 Data sheet ( Hoja de datos )
| Número de pieza | ZSSC1956 | |
| Descripción | Intelligent Battery Sensor IC | |
| Fabricantes | IDT | |
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Intelligent Battery Sensor IC
ZSSC1956
Datasheet
Brief Description
The ZSSC1956 IC is a dual-channel analog-to-digital
converter (ADC) with an embedded microcontroller
for battery sensing/management in automotive,
industrial, and medical systems.
One of the two input channels measures the battery
current IBAT via the voltage drop at the external
shunt resistor. The second input channel measures
the battery voltage VBAT and the temperature. An
integrated flash memory is provided for customer-
specific software; e.g., dedicated algorithms for
calculating the battery state.
During Sleep Mode (e.g., engine is off), the system
makes periodic measurements to monitor the dis-
charge of the battery. Measurement cycles are
controlled by the software and include various wake-
up conditions. The ZSSC1956 is optimized for ultra-
low power consumption and draws only 100µA or
less in Low-Power Mode.
Features
• High-precision 24-bit sigma-delta ADC (18-bit
with no missing codes); sample rate: 1Hz – 16kHz
• On-chip voltage reference (5ppm/K typical)
• Current channel
IBAT offset error: ≤ 10mA
IBAT resolution: ≤ 1mA
Programmable gain: 4 to 512
Differential input stage input range: ± 300mV
• Voltage channel
Input range: 4 to 28.8V
Voltage accuracy: better than ±2mV
• Temperature channel
Internal temperature sensor: ± 2°C
External temperature sensor (NTC)
• On-chip precision oscillator (1%) and on-chip
low-power oscillator
• ARM® Cortex™-M0* microcontroller:
32-bit core, 10MHz to 20MHz
• 96kB Flash/EE Memory with ECC, 8kB SRAM
• LIN2.2 / SAE J2602-2 compliant
• Directly connected to 12V battery supply
• Normal Mode current consumption: 10mA to 20mA
• Low-Power Mode current consumption: ≤ 100µA
© 2016 Integrated Device Technology, Inc.
Benefits
• Integrated, precision measurement solution for
accurate prediction of battery state of health
(SOH), state of charge (SOC) or state of function
(SOF)
• Flexible wake-up modes allow minimum power
consumption without sacrificing performance
• No temperature calibration or external trimming
components required
• Optimized code density through small instruction
set architecture Thumb®-2 *
• Robust power-on-reset (POR) concept for harsh
automotive environments
• Industry’s smallest footprint allows minimal
module size and cost
• AEC-Q100 qualified solution
Available Support
• Evaluation Kit
• Application Notes
Physical Characteristics
• Wide operation temperature: -40°C to +125°C
• Supply voltage: 4.2 to 18V
• Small footprint package: PQFN32 5x5 mm
Basic ZSSC1956 Application Circuit
+ -To Harness
Car Chassis Ground
Rshunt
+-
Battery
f
VBAT
VDDE
INP
INN
Host
LIN
Controller
LIN
Interface
VDDA ZSSC1956
NTH
NTC
NTL VSSA
GPIO
VSSE
5
Optional
GPIO:
SPI, I²C™,
UART
Module Ground
* The ARM®, Cortex™, and Thumb®-2 trademarks are owned by ARM, Ltd.
The I2C™ trademark is owned by NXP.
1 January 29, 2016
1 page  
ZSSC1956 Datasheet
4.5.4. Register Overview of GPIO Module .................................................................................................... 143
4.6. 32-Bit Timer ........................................................................................................................................... 145
4.6.1. Timer Mode ..................................................................................................................................... 145
4.6.2. Counter Mode ................................................................................................................................. 145
4.6.3. Timer Module Register Overview.................................................................................................... 146
4.7. LIN Communication Control Logic (ahbLIN).......................................................................................... 148
4.7.1. Functional Description .................................................................................................................... 149
4.7.2. Overview of Registers for LIN ahb Controller ................................................................................. 150
4.8. SPIB8..................................................................................................................................................... 163
4.8.1. Introduction ..................................................................................................................................... 163
4.8.2. SPI Signal Description .................................................................................................................... 164
4.8.3. Functional Description .................................................................................................................... 164
4.8.4. Interrupts and Status Flags............................................................................................................. 166
4.8.5. Overview of Registers for SPIB8 .................................................................................................... 167
4.9. SPI in ZSYSTEM2 ................................................................................................................................. 170
4.9.1. Data Transfers ................................................................................................................................ 170
4.9.2. Interrupts and Status Flags............................................................................................................. 171
4.9.3. Example of SPI Transfer Handling.................................................................................................. 172
4.9.4. Register Overview of SPI2.............................................................................................................. 174
4.10. I²C™ in ZSYSTEM2 .............................................................................................................................. 176
4.10.1. External Signal Lines ...................................................................................................................... 176
4.10.2. The I²C™ Bus ................................................................................................................................. 176
4.10.3. Bus Conflicts ................................................................................................................................... 177
4.10.4. Operating as Slave-Only................................................................................................................. 178
4.10.5. Operating as Single Master ............................................................................................................ 180
4.10.6. Operating as Master on a Multi-Master Bus ................................................................................... 181
4.10.7. Error Conditions .............................................................................................................................. 182
4.10.8. Bus States....................................................................................................................................... 182
4.10.9. Status Description ........................................................................................................................... 184
4.10.10. Register Overview for I²C™ Module ............................................................................................... 195
4.11. USART in ZSYSTEM2........................................................................................................................... 198
4.11.1. External Signal Lines ...................................................................................................................... 198
4.11.2. Asynchronous Mode ....................................................................................................................... 198
4.11.3. Synchronous Mode ......................................................................................................................... 200
4.11.4. Register Overview of USART ......................................................................................................... 202
5 ESD / EMC ................................................................................................................................................... 206
5.1. Electrostatic Discharge.......................................................................................................................... 206
5.2. Power System Ripple Factor ................................................................................................................. 206
© 2016 Integrated Device Technology, Inc.
5
January 29, 2016
5 Page 
ZSSC1956 Datasheet
Table 4.33
Table 4.34
Table 4.35
Table 4.36
Table 4.37
Table 4.38
Table 4.39
Table 4.40
Table 4.41
Table 4.42
Table 4.43
Table 4.44
Table 4.45
Table 4.46
Table 4.47
Table 4.48
Table 4.49
Table 4.50
Table 4.51
Table 4.52
Table 4.53
Table 4.54
Table 4.55
Table 4.56
Table 4.57
Table 4.58
Table 4.59
Table 4.60
Table 4.61
Table 4.62
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 6.1
Register LIN_RXDATA – system address 4000 1804HEX .............................................................. 153
Register LIN_TXDATA – system address 4000 1808HEX .............................................................. 153
Register LIN_HEADERLEN – system address 4000 180CHEX ....................................................... 153
Register LIN_BAUDRATE – system address 4000 1810HEX ........................................................... 154
Register LIN_BRKLOW – system address 4000 1814HEX ............................................................... 155
Register LIN_HINTERBRKDEL – system address 4000 1818HEX ................................................. 156
Register LIN_WAKEUPIDLE – system address 4000 181CHEX ..................................................... 157
Register LIN_IREN – system address 4000 1820HEX................................................................... 157
Register LIN_CLI – system address 4000 1824HEX..................................................................... 159
Register LIN_STAT – system address 4000 1828HEX................................................................... 161
Register SPICFG_B8 – system address 4000_2000HEX; local address is 00HEX............................ 167
Register SPICLKCFG_B8 – system address 4000_2004HEX; local address is 08HEX ..................... 168
Register SPISTAT_B8 – system address 4000_2008HEX; local address is 04HEX.......................... 168
Accessing the FIFO Buffers – system address 4000_XXXXHEX..................................................... 169
Register Z2_SPICFG – system address 4000 1C00HEX ................................................................. 174
Register Z2_SPIDATA – system address 4000 1C04HEX............................................................... 174
Register Z2_SPICLKCFG – system address 4000 1C08HEX........................................................... 175
Register Z2_SPISTAT – system address 4000 1C0CHEX .............................................................. 175
Register Z2_I2CCLKRATE – system address 4000 1C20HEX ........................................................ 195
Register Z2_I2CCLKRATE2 – system address 4000 1C24HEX ...................................................... 195
Register Z2_I2CADDR – system address 4000 1C28HEX............................................................... 195
Register Z2_I2CCTRL – system address 4000 1C2CHEX .............................................................. 196
Register Z2_I2CSTAT – system address 4000 1C30HEX............................................................... 197
Register Z2_I2CDATA – system address 4000 1C34HEX............................................................... 197
Register Z2_USARTCFG – system address 4000 1C40HEX............................................................. 202
Register Z2_USARTSTAT – system address 4000 1C44HEX........................................................... 203
Register Z2_USARTDATA – system address 4000 1C48HEX........................................................... 204
Register Z2_USARTIRQEN – system address 4000 1C4CHEX........................................................ 204
Register Z2_USARTCLK1 – system address 4000 1C50HEX.......................................................... 205
Register Z2_USARTCLK2 – system address 4000 1C54HEX........................................................... 205
Conducted Susceptibility ................................................................................................................ 207
Conducted Susceptibility on Power Supply Lines .......................................................................... 207
Conducted Susceptibility on Signal Lines....................................................................................... 207
Conducted Emission....................................................................................................................... 208
IC Pins ............................................................................................................................................ 210
© 2016 Integrated Device Technology, Inc.
11
January 29, 2016
11 Page | ||
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| PDF Descargar | [ Datasheet ZSSC1956.PDF ] | |
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