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PDF CAT24FC01UETE13REV-F Data sheet ( Hoja de datos )

Número de pieza CAT24FC01UETE13REV-F
Descripción 1-kb I2C Serial EEPROM
Fabricantes Catalyst Semiconductor 
Logotipo Catalyst Semiconductor Logotipo



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CAT24FC01
1-kb I2C Serial EEPROM
FEATURES
I 400 kHz (2.5 V) and 100 kHz (1.8 V) I2C bus
compatible
I 1.8 to 5.5 volt operation
I Low power CMOS technology
I 16-byte page write buffer
I Industrial and extended temperature ranges
I Self-timed write cycle with auto-clear
ALOGEN FR
LEA D F REETM
I 1,000,000 program/erase cycles
I 100 year data retention
I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and MSOP
packages
- “Green” package option available
I 256 x 8 memory organization
I Hardware write protect
DESCRIPTION
The CAT24FC01 is a 1-kb Serial CMOS EEPROM
internally organized as 128 words of 8 bits each. Catalyst’s
advanced CMOS technology substantially reduces
device power requirements.
The CAT24FC01 features a 16-byte page write buffer.
The device operates via the I2C bus serial interface and
is available in 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and
MSOP packages.
PIN CONFIGURATION
DIP Package (P, L)
SOIC Package (J, W)
A0
A1
A2
VSS
1
2
3
4
A0
A1
A2
VSS
8 VCC
A0
7 WP
A1
6 SCL
A2
5 SDA VSS
1
2
3
4
8
7
6
5
TSSOP Package (U, Y)
18
27
36
45
MSOP Package (R, Z)
VCC
WP
SCL
SDA
VCC
WP
SCL
SDA
A0
A1
A2
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC 1.8 V to 5.5 V Power Supply
VSS Ground
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
SDA
START/STOP
LOGIC
XDEC
E2PROM
WP CONTROL
LOGIC
SCL
A0
A1
A2
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry
the I2C Bus Protocol.
© 2004 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice.
1
Doc. No. 1073, Rev. D

1 page




CAT24FC01UETE13REV-F pdf
CAT24FC01
I2C BUS PROTOCOL
The following defines the features of the I2C bus proto-
col:
(1) Data transfer may be initiated only when the bus is
not busy.
(2) During a data transfer, the data line must remain
stable whenever the clock line is high. Any changes
in the data line while the clock line is high will be
interpreted as a START or STOP condition.
START Condition
The START Condition precedes all commands to the
device, and is defined as a HIGH to LOW transition of
SDA when SCL is HIGH. The CAT24FC01 monitors the
SDA and SCL lines and will not respond until this
condition is met.
STOP Condition
A LOW to HIGH transition of SDA when SCL is HIGH
determines the STOP condition. All operations must end
with a STOP condition.
DEVICE ADDRESSING
The Master begins a transmission by sending a START
condition. The Master then sends the address of the
particular slave device it is requesting. The four most
significant bits of the 8-bit slave address are fixed as
1010 for the CAT24FC01 (see Fig. 5). The next three
significant bits (A2, A1, A0) are the device address bits
Figure 4. Acknowledge Timing
SCL FROM
MASTER
1
and define which device the Master is accessing. Up to
eight CAT24FC01 may be individually addressed by the
system. The last bit of the slave address specifies
whether a Read or Write operation is to be performed.
When this bit is set to 1, a Read operation is selected,
and when set to 0, a Write operation is selected.
After the Master sends a START condition and the slave
address byte, the CAT24FC01 monitors the bus and
responds with an acknowledge (on the SDA line) when
its address matches the transmitted slave address. The
CAT24FC01 then performs a Read or a Write operation
depending on the state of the R/W bit.
Acknowledge
After a successful data transfer, each receiving device is
required to generate an acknowledge. The Acknowledg-
ing device pulls down the SDA line during the ninth clock
cycle, signaling that it received the 8 bits of data.
The CAT24FC01 responds with an acknowledge after
receiving a START condition and its slave address. If the
device has been selected along with a write operation,
it responds with an acknowledge after receiving each
byte.
When the CAT24FC01 begins a READ mode, it trans-
mits 8 bits of data, releases the SDA line, and monitors
the line for an acknowledge. Once it receives this ac-
knowledge, the CAT24FC01 will continue to transmit
data. If no acknowledge is sent by the Master, the device
terminates data transmission and waits for a STOP
condition.
89
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
Figure 5. Slave Address Bits
ACKNOWLEDGE
1 0 1 0 A2 A1 A0 R/W Normal Read and Write
DEVICE ADDRESS
5 Doc No. 1073, Rev. D

5 Page










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