PDF AD7761 Data sheet ( Hoja de datos )

Número de pieza	AD7761
Descripción	Simultaneous Sampling ADC
Fabricantes	Analog Devices
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Data Sheet 8-Channel, 16-Bit, Simultaneous Sampling ADC with Power Scaling, 110.8 kHz BW AD7761 FEATURES Linear phase digital filter Precision ac and dc performance 8-channel simultaneous sampling 256 kSPS ADC output data rate per channel 97.7 dB dynamic range 110.8 kHz input bandwidth (−3 dB bandwidth (BW)) –120 dB THD, typical ±1 LSB INL, ±1 LSB offset error, ±5 LSB gain error Optimized power dissipation vs. noise vs. input bandwidth Low latency sinc5 filter Wideband brick wall filter: ±0.005 dB ripple to 102.4 kHz Analog input precharge buffers Power supply AVDD1 = 5 V, AVDD2 = 2.25 V to 5.0 V IOVDD = 2.5 V to 3.3 V or IOVDD = 1.8 V 64-lead LQFP package, no exposed pad Temperature range: −40°C to +105°C Selectable power, speed, and input bandwidth Fast: highest speed; 110.8 kHz BW, 51.5 mW per channel Median: half speed, 55.4 kHz BW, 27.5 mW per channel Focus: lowest power, 13.8 kHz BW, 9.375 mW per channel Input BW range: dc to 110.8 kHz Programmable input bandwidth/sampling rates Cyclic redundancy check (CRC) error checking on data interface Daisy-chaining APPLICATIONS Data acquisition systems: USB/PXI/Ethernet Instrumentation and industrial control loops Audio test and measurement Vibration and asset condition monitoring 3-phase power quality analysis Sonar High precision medical electroencephalogram (EEG)/ electromyography (EMG)/electrocardiogram (ECG) FUNCTIONAL BLOCK DIAGRAM AVDD1A, AVDD1B REFx+ REFx– AVDD2A, REGCAPA, AVDD2B REGCAPB DGND IOVDD DREGCAP VCM BUFFERED VCM VCM PRECHARGE ×8 REFERENCE BUFFERS 1.8V LDO AIN0+ CH 0 AIN0– AIN1+ CH 1 AIN1– AIN2+ CH 2 AIN2– AIN3+ CH 3 AIN3– AIN4+ CH 4 AIN4– AIN5+ CH 5 AIN5– AIN6+ CH 6 AIN6– P P P P P P P P P P P P P P Σ-∆ ADC Σ-∆ ADC Σ-∆ ADC Σ-∆ ADC Σ-∆ ADC Σ-∆ ADC Σ-∆ ADC DIGITAL FILTER ENGINE SINC5 LOW LATENCY FILTER WIDEBAND LOW RIPPLE FILTER OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION OFFSET, GAIN PHASE CORRECTION 1.8V LDO ADC OUTPUT DATA SERIAL INTERFACE SPI CONTROL INTERFACE SYNC_IN SYNC_OUT START RESET FORMAT1 FORMAT0 DRDY DCLK DOUT0 DOUT1 DOUT2 DOUT3 DOUT4 DOUT5 DOUT6 DOUT7 ST0/CS ST1/SCLK DEC0/SDO DEC1/SDI AIN7+ CH 7 AIN7– P Σ-∆ P ADC ×16 ANALOG INPUT PRECHARGE BUFFERS (P) OFFSET, GAIN PHASE CORRECTION AD7761 PIN/SPI AVSS XTAL2/MCLK Figure 1. XTAL1 MODE3/GPIO3 FILTER/GPIO4 TO MODE0/GPIO0 Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page AD7761 Data Sheet SPECIFICATIONS AVDD1A = AVDD1B = 4.5 V to 5.5 V, AVDD2A = AVDD2B = 2.0 V to 5.5 V, IOVDD = 1.72 V to 1.88 V and 2.25 V to 3.6 V, AVSS = DGND = 0 V, REFx+ = 4.096 V and REFx− = 0 V, MCLK = 32.768 MHz, analog input precharge buffers on, reference precharge buffers off, wideband filter, fCHOP = fMOD/32, TA = −40°C to +105°C, unless otherwise noted. Table 1. Parameter ADC SPEED AND PERFORMANCE Output Data Rate (ODR), per Channel1 −3 dB Bandwidth Data Output Coding No Missing Codes2 DYNAMIC PERFORMANCE Dynamic Range Signal-to-Noise Ratio (SNR) Signal-to-Noise-and-Distortion Ratio (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) INTERMODULATON DISTORTION (IMD) ACCURACY INL3 Offset Error4 Gain Error4 Gain Drift vs. Temperature2 VCM PIN Output Test Conditions/Comments Fast Median Focus Fast, wideband filter Median, wideband filter Focus, wideband filter Decimation by 32, 256 kSPS ODR Shorted input, wideband filter 1 kHz, −0.5 dBFS, sine wave input Sinc5 filter Wideband filter 1 kHz, −0.5 dBFS, sine wave input 1 kHz, −0.5 dBFS, sine wave input fINA = 9.7 kHz, fINB = 10.3 kHz Second order Third order Endpoint method TA = 25°C With respect to AVSS Load Regulation Voltage Regulation Short-Circuit Current ANALOG INPUTS Differential Input Voltage Range Input Common-Mode Range2 Absolute Analog Input Voltage Limits2 Analog Input Current Unbuffered Precharge Buffer On5 Input Current Drift Unbuffered Precharge Buffer On ∆VOUT/∆IL Applies to the following VCM output options only: VCM = ∆VOUT/∆(AVDD1 − AVSS)/2, VCM = 1.65 V, and VCM = 2.5 V See the Analog Input section VREF = (REFx+) − (REFx−) Differential component Common-mode component Min Typ Max 8 256 4 128 1 32 110.8 55.4 13.8 Twos complement, MSB first 16 97.3 97.3 97.3 97.3 −VREF AVSS AVSS 97.7 97.9 97.7 97.7 −120 126 −107 −125 −124 ±1 ±1 ±5 ±0.01 (AVDD1 − AVSS)/2 400 5 ± 1.5 ±2 ±40 ±0.02 30 +VREF AVDD1 AVDD1 ±48 ±17 −20 ±5 ±31 Unit kSPS kSPS kSPS kHz kHz kHz Bits dB dB dB dB dB dBc dB dB LSB LSB LSB LSB/°C V μV/mA μV/V mA V V V μA/V μA/V μA nA/V/°C nA/°C Rev. 0 \| Page 4 of 69 5 Page AD7761 Data Sheet Parameter t9 t10 t11 t12 t13 t14 Description DCLK low time DCLK = MCLK/1 t9a = DCLK = MCLK/2 t9b = DCLK = MCLK/4 t9c = DCLK = MCLK/8 MCLK rising to DCLK rising Setup time of DOUT6 and DOUT7 Hold time of DOUT6 and DOUT7 START low time MCLK to SYNC_OUT valid t15 SYNC_IN setup time t16 SYNC_IN hold time Test Conditions/Comments Min 50:50 CMOS clock (tDCLK/2) − 5 CMOS clock CMOS clock SYNC_OUT RETIME_EN bit disabled; measured from falling edge of MCLK SYNC_OUT RETIME_EN bit enabled; measured from rising edge of MCLK CMOS clock CMOS clock 14 0 1 × tMCLK 4.5 9.5 0 10 Typ tMCLK/2 tMCLK 2 × tMCLK 4 × tMCLK Max tDCLK/2 30 22 27.5 1 These specifications are not production tested but are supported by characterization data at initial product release. Table 3. SPI Control Interface Timing1 Parameter Description t17 SCLK period t18 CS falling edge to SCLK rising edge t19 SCLK falling edge to CS rising edge t20 CS falling edge to data output enable t21 SCLK high time t22 SCLK low time t23 SCLK falling edge to SDO valid t24 SDO hold time after SCLK falling t25 SDI setup time t26 SDI hold time t27 SCLK enable time t28 SCLK disable time t29 CS high time t30 CS low time Test Conditions/Comments fMOD = MCLK/4 fMOD = MCLK/8 fMOD = MCLK/32 Min 100 26.5 27 22.5 20 20 7 0 6 0 0 10 1.1 × tMCLK 2.2 × tMCLK 8.8 × tMCLK Typ 50 50 Max 40.5 15 1 These specifications are not production tested but are supported by characterization data at initial product release. Unit ns ns ns ns ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.8 V IOVDD TIMING SPECIFICATIONS AVDD1A = AVDD1B = 5 V, AVDD2A = AVDD2B = 5 V, IOVDD = 1.72 V to 1.88 V (DREGCAP tied to IOVDD), Input Logic 0 = DGND, Input Logic 1 = IOVDD, CLOAD = 10 pF on DCLK pin, CLOAD = 20 pF on other digital outputs, TA = −40°C to +105°C. Table 4. Data Interface Timing1 Parameter Description MCLK Master clock fMOD Modulator frequency t1 DRDY high time t2 DCLK rising edge to DRDY rising edge Test Conditions/Comments Fast mode Median mode Focus mode Min 1.15 tDCLK − 10% Typ MCLK/4 MCLK/8 MCLK/32 28 Max 34 2 Unit MHz Hz Hz Hz ns ns Rev. 0 \| Page 10 of 69 11 Page

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