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PDF P6408T2B5X2 Data sheet ( Hoja de datos )
| Número de pieza | P6408T2B5X2 | |
| Descripción | Embedded MCP | |
| Fabricantes | Apollo | |
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eMCP Specification
Embedded MCP specification
P6408T2B5X2
Datasheet Preliminary Ver 1.0
Apollo Memory System Company
____________________________________________________________________________________________________________________
© 2014 Apollo memory system company
1
CONFIDENTIAL
1 page  
eMCP Specification
1.2. e•MMC™ Device Overview
The e•MMC™ device transfers data via a configurable number of data bus signals. The communication
signals are:
1.2.1 Clock (CLK)
Each cycle of this signal directs a one bit transfer on the command and either a one bit (1x) or a two
bits transfer (2x) on all the data lines. The frequency may vary between zero and the maximum clock
frequency.
1.2.2 Command (CMD)
This signal is a bidirectional command channel used for Device initialization and transfer of
commands. The CMD signal has two operation modes: open-drain for initialization mode, and push-
pull for fast command transfer. Commands are sent from the e•MMC™ host controller to the
e•MMC™ Device and responses are sent from the Device to the host.
1.2.3 Input/Outputs (DAT0-DAT7)
These are bidirectional data channels. The DAT signals operate in push-pull mode. Only the Device or
the host is driving these signals at a time. By default, after power up or reset, only DAT0 is used for
data transfer. A wider data bus can be configured for data transfer, using either DAT0-DAT3 or DAT0-
DAT7, by the e•MMC™ host controller. The e•MMC™ Device includes internal pull-ups for data lines
DAT1-DAT7. Immediately after entering the 4-bit mode, the Device disconnects the internal pull ups
of lines DAT1, DAT2, and DAT3. Correspondingly, immediately after entering to the 8-bit mode the
Device disconnects the internal pull-ups of lines DAT1–DAT7.The signals on the e•MMC™ interface are
described in Table 3.
Table 3 – e•MMC™ Interface
Name
Type1
Description
CLK I
Clock
DAT0
I/O/PP
Data
DAT1
I/O/PP
Data
DAT2
I/O/PP
Data
DAT3
I/O/PP
Data
DAT4
I/O/PP
Data
DAT5
I/O/PP
Data
DAT6
I/O/PP
Data
DAT7
I/O/PP
Data
CMD
I/O/PP/OD
Command/Response
RST_n
I
Hardware reset
VCC S
Supply voltage for Core
VCCQ
S
Supply voltage for I/O
VSS S
Supply voltage ground for Core
VSSQ
S
Supply voltage ground for I/O
Note1：I: input; O: output; PP: push-pull; OD: open-drain; NC: Not connected (or logical high); S: power supply.
Each Device has a set of information registers (see also 0, Device Registers.)
____________________________________________________________________________________________________________________
© 2014 Apollo memory system company
5
CONFIDENTIAL
5 Page 
eMCP Specification
3.1. Power-up
3.1.1 e•MMC™ power-up
An e•MMC™ bus power-up is handled locally in each device and in the bus master. Figure 6 shows
the power-up sequence and is followed by specific instructions regarding the power-up sequence.
Refer to section 10.1 of the JEDEC Standard Specification No.JESD84-B50 for specific instructions
regarding the power-up sequence.
Figure 6 – e•MMC™ Power-up Diagram
____________________________________________________________________________________________________________________
© 2014 Apollo memory system company
11
CONFIDENTIAL
11 Page | ||
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