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PDF IDT70V9199L Data sheet ( Hoja de datos )

Número de pieza IDT70V9199L
Descripción HIGH-SPEED 3.3V 128K x9/x8 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Fabricantes IDT 
Logotipo IDT Logotipo



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No Preview Available ! IDT70V9199L Hoja de datos, Descripción, Manual

HIGH-SPEED 3.3V
128K x9/x8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
IDT70V9199/099L
Features:
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial: 6/7.5/9/12ns (max.)
– Industrial: 9ns (max.)
Low-power operation
– IDT70V9199/099L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pins
Dual chip enables allow for depth expansion without
additional logic
Counter enable and reset features
Full synchronous operation on both ports
– 3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
– Data input, address, and control registers
– Fast 6.5ns clock to data out in the Pipelined output mode
– Self-timed write allows fast cycle time
– 10ns cycle time, 100MHz operation in Pipelined output mode
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
OEL
CE0L
CE1L
1
0
0/1
R/WR
OER
CE0R
1 CE1R
0
0/1
FT/PIPEL
I/O0L - I/O8L(1)
0/1 1
0
I/O
Control
I/O
Control
0 1 0/1
FT/PIPER
I/O0R - I/O8R(1.)
A16L
A0L
CLKL
ADSL
CNTENL
CNTRSTL
NOTE:
1. I/O0X - I/O7X for IDT70V9099.
Counter/
Address
Reg.
©2003 Integrated Device Technology, Inc.
MEMORY
ARRAY
1
Counter/
Address
Reg.
A16R
A0R
CLKR
ADSR
CNTENR
CNTRSTR
4859 drw 01
APRIL 2003
DSC-4859/3

1 page




IDT70V9199L pdf
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage(1)
Grade
Ambient
Temperature(2)
GND
VDD
Commercial
0OC to +70OC 0V 3.3V + 0.3V
Industrial
-40OC to +85OC
0V
3.3V + 0.3V
NOTES:
4859 tbl 04
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions
Symbol
Parameter
Min. Typ.
Max.
Unit
VDD Supply Voltage
3.0 3.3
3.6
V
VSS Ground
00
0V
VIH Input High Voltage
2.0 ____ VDD+0.3V(2) V
VIL Input Low Voltage
-0.3(1)
____
0.8
V
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDD +0.3V.
4859 tbl 05
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
VTERM(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
TBIAS(3)
Temperature
Under Bias
-55 to +125
oC
TSTG
Storage
Temperature
-65 to +150
oC
TJN Junction Temperature
+150
oC
IOUT DC Output Current
50 mA
NOTES:
4859 tbl 06
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under DC Bias. No AC Conditions. Chip deselect.
Capacitance(1)
(TA = +25°C, f = 1.0MHZ)
Symbol
Parameter
Conditions(2)
Max. Unit
CIN Input Capacitance
VIN = 3dV
9 pF
COUT(3) Output Capacitance
VOUT = 3dV
10 pF
NOTES:
4859 tbl 07
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
Symbol
Parameter
|ILI| Input Leakage Current(1)
|ILO| Output Leakage Current
VOL Output Low Voltage
VOH Output High Voltage
Test Conditions
VDD = 3.6V, VIN = 0V to VDD
CE = VIH or CE1 = VIL, VOUT = 0V to VDD
IOL = +4mA
IOH = -4mA
NOTE:
1. At VDD < 2.0V input leakages are undefined.
70V9199/099L
Min. Max. Unit
___ 5 µA
___ 5 µA
___ 0.4 V
2.4 ___ V
4859 tbl 08
6.452

5 Page





IDT70V9199L arduino
IDT70V9199/099L
High-Speed 3.3V 128K x9/x8 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
R/W
ADDRESS(4)
DATAIN
DATAOUT
tSC tHC
tSW tHW
An
tSA tHA
An +1
tCD2
(2)
READ
tSW tHW
An + 2
An + 2
tSD tHD
An + 3
Dn + 2
tCKHZ (1)
Qn
NOP(5)
WRITE
An + 4
tCKLZ(1)
tCD2
Qn + 3
READ
4859 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
tCYC2
tCH2
tCL2
CLK
CE0
CE1
R/W
tSC tHC
tSW tHW
tSW tHW
ADDRESS(4)
DATAIN
DATAOUT
An
tSA tHA
(2)
An +1
An + 2
tSD tHD
Dn + 2
tCD2
Qn
tOHZ(1)
An + 3
Dn + 3
An + 4
An + 5
tCKLZ(1)
tCD2
Qn + 4
OE
READ
WRITE
READ
4859 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1412

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