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PDF IDT70T3399 Data sheet ( Hoja de datos )

Número de pieza IDT70T3399
Descripción HIGH-SPEED 2.5V 512/256/128K x 18 SYNCHRONOUS DUAL-PORT STATIC RAM
Fabricantes IDT 
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No Preview Available ! IDT70T3399 Hoja de datos, Descripción, Manual

HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
Š WITH 3.3V OR 2.5V INTERFACE
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
– Data input, address, byte enable and control registers
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timed write allows fast cycle time
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V (±100mV) power supply for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Functional Block Diagram
UBL
LBL
UBR
LBR
FT/PIPEL
R/WL
CE0L
CE1L
OEL
0a 1a 0b 1b
1/0
ab
1
0
1/0
BB
WW
01
LL
Dout0-8_L
Dout9-17_L
BB
WW
10
RR
Dout0-8_R
Dout9-17_R
1b 0b
b
1a 0a
a
1/0
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
FT/PIPEL
1b 0b 1a 0a
0/1
ab
512/256/128K x 18
MEMORY
ARRAY
0a 1a 0b
1b
ba
0/1
FT/PIPER
,
I/O0L - I/O17L
Din_L
Din_R
I/O0R - I/O17R
CLKL
A18L(1)
A0L
REPEATL
ADSL
CNTENL
COL L
INTL
Counter/
Address
Reg.
CE 0 L
CE 1L
R/W L
ADDR_L
ADDR_R
INTERRUPT
COLLISION
DETECTION
LOGIC
ZZL(2)
ZZ
CO NTRO L
LOGIC
Counter/
Address
Reg.
R/WR
CE0 R
CE1R
ZZR(2)
CLKR
A18R(1)
A0R
REPEATR
ADSR
CNTENR
TDI
TDO
COLR
INTR
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
©2015 Integrated Device Technology, Inc.
1
,
TCK
JTAG TMS
TRST
5652 drw 01
JUNE 2015
DSC-5652/8

1 page




IDT70T3399 pdf
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Pin Names
Left Port
Right Port
CE0L, CE1L
R/WL
CE0R, CE1R
R/WR
OEL
A0L - A18L(5)
OER
A0R - A18R(5)
I/O0L - I/O17L
I/O0R - I/O17R
CLKL
PL/FTL
CLKR
PL/FTR
ADSL
ADSR
CNTENL
CNTENR
REPEATL
REPEATR
UBL UBR
LBL
VDDQL
LBR
VDDQR
OPTL
OPTR
ZZL ZZR
VDD
VSS
TDI
TDI
TCK
TMS
TRST
INTL
COLL
INTR
COLR
Names
Chip Enables (Input)(6)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
Data Input/Output
Clock (Input)
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat(3)
Upper Byte Enable (I/O9 - I/O17)(6)
Lower Byte Enable (I/O0 - I/O8)(6)
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode pin(4) (Input)
Power (2.5V)(1) (Input)
Ground (0V) (Input)
Test Data Input
Test Data Output
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
Collision Alert (Output)
5652 tbl 01
Industrial and Commercial Temperature Ranges
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5. Address A18x is a NC for the IDT70T3319. Also, Addresses A18x and A17x are
NC's for the IDT70T3399.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.542

5 Page





IDT70T3399 arduino
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T3339/19/99
S200
Com'l Only(5)
70T3339/19/99
S166
Com'l
& Ind(4)
70T3339/19/99
S133
Com'l
& Ind
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
tCYC1
Clock Cycle Time (Flow-Through)(1)
15 ____ 20 ____ 25 ____ ns
tCYC2
Clock Cycle Time (Pipelined)(1)
5 ____ 6 ____ 7.5 ____ ns
tCH1 Clock High Time (Flow-Through)(1)
6 ____ 8 ____ 10 ____ ns
tCL1 Clock Low Time (Flow-Through)(1)
6 ____ 8 ____ 10 ____ ns
tCH2 Clock High Time (Pipelined)(2)
2 ____ 2.4 ____ 3 ____ ns
tCL2 Clock Low Time (Pipelined)(1)
2 ____ 2.4 ____ 3 ____ ns
tSA Address Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHA Address Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSC Chip Enable Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHC Chip Enable Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSB Byte Enable Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHB Byte Enable Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSW R/W Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHW R/W Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSD Input Data Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHD Input Data Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSAD ADS Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHAD ADS Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSCN CNTEN Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHCN CNTEN Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tSRPT
REPEAT Setup Time
1.5 ____ 1.7 ____ 1.8 ____ ns
tHRPT
REPEAT Hold Time
0.5 ____ 0.5 ____ 0.5 ____ ns
tOE Output Enable to Data Valid
____ 4.4 ____ 4.4 ____ 4.6 ns
tOLZ(6)
Output Enable to Output Low-Z
1 ____
1 ____
1 ____ ns
tOHZ(6)
Output Enable to Output High-Z
1 3.4
1 3.6
1 4.2 ns
tCD1 Clock to Data Valid (Flow-Through)(1)
____ 10 ____ 12 ____ 15 ns
tCD2 Clock to Data Valid (Pipelined)(1)
____ 3.4 ____ 3.6 ____ 4.2 ns
tDC Data Output Hold After Clock High
1 ____
1 ____
1 ____ ns
tCKHZ(6)
Clock High to Output High-Z
1 3.4
1 3.6
1 4.2 ns
tCKLZ(6)
Clock High to Output Low-Z
1 ____
1 ____
1 ____ ns
tINS Interrupt Flag Set Time
____ 7 ____ 7 ____ 7 ns
tINR Interrupt Flag Reset Time
____ 7 ____ 7 ____ 7 ns
tCOLS
Collision Flag Set Time
____ 3.4 ____ 3.6 ____ 4.2 ns
tCOLR
Collision Flag Reset Time
____ 3.4 ____ 3.6 ____ 4.2 ns
tZZSC
Sleep Mode Set Cycles
2 ____ 2 ____ 2 ____ cycles
tZZRC
Sleep Mode Recovery Cycles
3 ____ 3 ____ 3 ____ cycles
Port-to-Port Delay
tCO Clock-to-Clock Offset
4 ____ 5 ____ 6 ____ ns
tOFS Clock-to-Clock Offset for Collision Detection
Please refer to Collision Detection Timing Table on Page 20
5652 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 package.
6. Guaranteed by design (not production tested).
61.412

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