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PDF EL320.240-FA3 Data sheet ( Hoja de datos )
| Número de pieza | EL320.240-FA3 | |
| Descripción | Multi-Color QVGA EL Display | |
| Fabricantes | Planar Systems | |
| Logotipo |  |
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EL320.240-FA3
Multi-Color QVGA EL Display
OPERATIONS MANUAL
www.planar.com
1 page  
Installation and Set-up
Do not drop, bend, or flex the display. Do not allow objects to strike the
surface of the display.
CAUTION: The display uses CMOS and devices. These components are
electrostatic-sensitive. Unpack, assemble, and examine this assembly in a
static-controlled area only. When shipping, use packing materials designed
for protection of electrostatic-sensitive components.
Mounting EL Displays
Properly mounted, EL displays can withstand high shock loads as well as
severe vibration found in demanding applications. However the glass panel
used in an EL display will break if subjected to bending stresses, high impact,
or excessive loads.
Avoid bending the display. Stresses are often introduced when a display is
mounted into a product. Ideally, the mounting tabs of the display should be
the only point of contact with the system. Use a spacer or boss for support;
failure to do so will bend the display and cause the glass to break. The
instrument enclosure or frame should not flex or distort in such a way that
during use the bending loads might be transferred to the display. The
EL320.240-FA3 mounting tabs were designed for a 3 mm screw. Mounting
surfaces should be flat to within ±0.6 mm (±0.025"). Use all the mounting holes
provided. Failure to do so will impair the shock and vibration resistance of the
final installation.
WARNING: These products generate voltages capable of causing personal
injury (high voltage up to 140 Vac ). Do not touch the display electronics
during operation.
Cable Length
A cable length of 0.5 m (20 inches) or less is recommended. Longer cables may
cause visual artifacts such as pixel “jitter” due to data transfer problems
between the host and the display.
Cleaning
As with any glass surface, care should be taken to minimize scratching. Clean
the display glass with mild, water-based detergents only. Apply the cleaner
sparingly to a soft cloth, then wipe the display. Disposable cleaning cloths are
recommended to minimize the risk of inadvertently scratching the display
with particles embedded in a re-used cloth.
EL320.240-FA3 Operations Manual
Page 5 of 25
5 Page 
Display Interface
The display supports five video interface modes: SGD timing as used on the
Planar EL320.240.36-HB (though with video data differences to denote colors)
and the four AMLCD timing modes used on Sharp and Kyocera QVGA color
displays (though using only two bits of red and green data). Four bits of data
per pixel are provided. The data is clocked to the display with a video clock,
VCLK. Frame and line synchronization is provided by the VS, HS and (if needed)
DE signals.
Video mode detection is performed automatically. The display evaluates the
timing of the incoming video approximately every 25 msec and will shift “on
the fly” between video modes as required.
The internal display controller utilizes a frame buffer to provide the display
with the appropriate modulation on a line by line and frame by frame basis to
implement the color generation, including frame dithering algorithms. Thus
the input frame rate and the display scan rate, in general, will not be the same
and will not be synchronous.
Video Mode Selection
Inputs LUM0 and LUM1 must be set to attain the desired video mode as shown
in the following table.
LUM0 and
LUM1 = 1?
No
No
No
No
No
Yes
V/Q
Input
0
0
1
1
X
X
DE
Input
Active
0
Active
0
1
X
Mode
Name
AMLCD,Q
VGA
AMLCD,
QVGA,
Fixed
AMLCD,
VGA
AMLCD,
VGA,
Fixed
SGD
Self test
Mode Description
(refer to Video Mode Timing for details)
AMLCD timing. DE determines the
horizontal location of data.
AMLCD timing. Horizontal start of valid
data is a predetermined number of VCLKs
from HS.
AMLCD timing. Displays upper left
quadrant of a VGA (640x480) input signal
with DE determining the horizontal
location of data.
AMLCD timing. Displays upper left
quadrant of a VGA (640x480) input signal
with the horizontal start of valid data
predetermined.
SGD timing. Horizontal start of valid data is
the first VCLK after HS.
Displays various patterns at the maximum
refresh rate regardless of video input data.
Useful for verifying display functionality.
Note:1) DE is considered active if more than eight logic transitions are detected
2) SGD mode is similar to that of the Planar EL320.240.36 and EL320.240-HB
displays but with required changes to the video data content to represent color
3) The AMLCD modes are compatible with those found on the following QVGA
displays though the video data content of 4 bits/pixel is a subset of the typical
18 bits/pixel: Sharp LQ057Q3DC12, Sharp LQ057Q3DC02, Kyocera
TCG057QV1AC
EL320.240-FA3 Operations Manual
Page 11 of 25
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet EL320.240-FA3.PDF ] | |
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