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PDF UPD8253-5 Data sheet ( Hoja de datos )

Número de pieza UPD8253-5
Descripción PROGRAMMABLE INTERVAL TIMER
Fabricantes NEC 
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No Preview Available ! UPD8253-5 Hoja de datos, Descripción, Manual

NEe Microcomputers, Inc.
PROGRAMMABLE INTERVAL TIMER
NEe
p.PD8253
p.PD8253-5
DESCR IPTION
The NEC flPD8253-5 contains three independent, programmable, multi-modal 16-bit
counter/timers. It is designed as a general purpose device, fully compatible with the
8080 family. The flPD8253-5 interfaces directly to the busses of the processor as an
array of I/O ports.
The flPD8253-5 can generate accurate time delays und~r the control of system software.
The three independent 16-bit counters can be clocked at rates from DC to 4 MHz.
The system software controls the loading and starting of the counters to provide
accurate multiple time delays. The counter output flags the processor at the comple-
tion of the time-out cycles.
System overhead is greatly improved by relieving the software from the maintenance
of timing loops. Some other common uses for the flPD8253,5 in microprocessor based
systems are:
• Programmable Baud Rate Generator
• Event Counter
• Binary Rate Multiplier
• Real Time Clock
• Digital One-Shot
• Complex Motor Controller
• NEC Now Supplies flPD8253-5 to all flPD8253 Requirements
F EATU RES
Three Independent 16-Bit Counters
• Clock Rate: DC to 4 MHz
• Count Binary or BCD
• Single +5 Volt Supply, ±10%
• 24 Dual-In-Line Plastic Package
PIN CONFIGURATION
07
06 2
24 VCC
23 WR
05 3
22 RO
04 4
21 CS
03 5
20 A1
02 6
01
DO 8
j.LPD
8253-5
19
18
17
AO
CLK 2
OUT2
CLK 0 9
16 GATE 2
OUTO 10
15 CLK 1
GATEO 11
14 GATE 1
GNO 12
13 OUT 1
07-0 0
CLK N
GATE N
OUT N
RO
WR
CS
AO,A1
VCC
G~O
PIN NAMES
Data Bus 18-Bitl
Counter Clock Inputs
Counter Gate Inputs
Counter Outputs
Read Counter
Write Command or Data
Chip Select
Counter Select
+5 Volts
Ground
II
Rev/4
601

1 page




UPD8253-5 pdf
f-L PD8253-5
PROGRAMMING
THE /lPD8253-5
The programmer can select any of the six operational MODES for the counters using
system software. Individual counter programming is accomplished by loading the
CONTRO L WOR DR EGISTER with the appropriate control word data iAO, A 1 = 111.
CONTROL WORD FORMAT
SC - Select Counter
SC1 SCO
0 0 Select Counter 0
0 1 Select Counter 1
1 0 Select Counter 2
1 1 Invalid
R L - Read/Load
RL1 RLO
00
10
01
11
Counter Latching Operation
Read/Load Most Significant Byte Only
Read/Load Least Significant Byte Only
Re~d/Load Least Significant Byte First, Then Most
Significant Byte
BCD
Binary Counter, 16-Bits
BCD Counter, 4-Decades
M-Mode
M2 M1 MO
0 0 0 Mode 0
0 0 1 Mode 1
X 1 0 Mode 2
X 1 1 Mode 3
1 0 0 Mode 4
1 0 1 Mode 5
II
605

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