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PDF THCV226 Data sheet ( Hoja de datos )

Número de pieza THCV226
Descripción HS High-speed Video Data Receiver
Fabricantes THine Electronics 
Logotipo THine Electronics Logotipo



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THCV226_Rev.1.10_E
THCV226
V-by-One® HS High-speed Video Data Receiver
General Description
THCV226 is designed to support video data
transmission between the host and display. This chip
can receive 32bit video data and 3bit control data via
four differential pairs of V-by-One® HS lanes. This
chip in TQFP package supports the video data
transmission up to 1080p/10b/120Hz. The maximum
serial data rate is 3.4Gbps/lane.
Block Diagram
Features
Normal / High-speed LVDS output selectable
1.8V single power supply
Color depth selectable: 8/10 bits per colors
Crossing / Distribution mode selectable
Monitoring signal function
1.8V LVTTL I/O interface
Package: 128pin 0.4mm-pitch TQFP
(16mm x 16mm)
Wide frequency range
AC coupling for CML inputs
CDR requires no external frequency reference
Supports Spread Spectrum Clocking tolerance
with up to 30kHz/0.5%(center spread)
V-by-One® HS standard compliant
PLL requires no external components
Power down / Output enable mode
VDD
(1.8V)
Rx0p
Rx0n
Rx1p
Rx1n
Rx2p
Rx2n
Rx3p
Rx3n
HTPDN
LOCKN
BETOUT
DGLOCK
Controls
RLA0p/n
RLE0p/n
RLCLK0p/n
RLA1p/n
RLE1p/n
RLCLK1p/n
RLA2p/n
RLE2p/n
RLCLK2p/n
RLA3p/n
RLE3p/n
RLCLK3p/n
Data Transmission Rate of CML Input
Color
Depth
Normal Speed
LVDS Mode
High-Speed
LVDS Mode
8bit
1.2 to 2.7Gbps
1.2 to 2.36Gbps
10bit
1.6 to 3.4Gbps
1.6 to 3.14Gbps
Clock Frequency of LVDS Output
Color
Depth
Normal Speed
LVDS Mode
High-Speed
LVDS Mode
8bit
40 to 90MHz
80 to 157MHz
10bit
40 to 85MHz
80 to 157MHz
Color Depth
Transmission Mode Setting
Power Down
Output Enable
Monitoring Signal Setting
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THCV226 pdf
THCV226_Rev.1.10_E
Functional Description
Functional Overview
With V-by-One® HSs proprietary encoding scheme and CDR (Clock and Data Recovery) architecture,
THCV226 enables the transmission of 8 or 10-bit video data, 2-bit synchronizing control data of HSYNC,
VSYNC, and Data Enable(DE), by a pair cable with minimal external components.
THCV226 automatically extracts the clock from the incoming data streams and converts the serial data into
video data with DE being high or synchronizing control data with DE being low, recognizing which type of
serial data is being sent by the transmitter. Also, THCV226 outputs the recovered data in the LVDS data format.
THCV226 can operate for a wide range of a serial bit rate from 1.2Gbps to 3.4Gbps. It is unnecessary to use
any external frequency reference, such as a crystal oscillator.
Data Enable Requirement (DE)
There are some requirements for DE signal as described in Figure1 and Figure2.
If DE=Low, control data of same cycle and particular assigned data bit ‘CTL’ except the first and last pixel are
transmitted. Otherwise video data is transmitted during DE=High.
Control data from source device in DE=High period is previous data of DE transition. See Figure2.
The length of DE being low and high must be at least 8 clock cycles long, as described in Figure17 and Table17.
DE must be toggled as High -> Low -> High at regular interval.
CTL Bit Transmission
There is particular assigned data bit ‘CTL’ which can be transmitted at blanking period except the first and the
last pixel on DE=Low.
Transmitter
Data bit : R/G/B, CONT
1
THCV226
R/G/B
CONT
CTL
DE=1 , R/G/B, CONT
DE=0 , CTL* except the 1st and the last pixel
Other R/G/B, CONT=Low Fixed.
Control bit : HSYNC, VSYNC
Data bit : CTL*
0
VSYNC
HSYNC
DE=1 , HSYNC, VSYNC=Fixed
DE=0 , HSYNC, VSYNC
DE DE
CTL* are particular assigned bits among R/G/B, CONT that can carry arbitrary data during DE=Low period.
Figure 1. Conceptual Diagram of Basic Operation of Chipset
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THCV226 arduino
THCV226_Rev.1.10_E
LVDS Output Enable Function
By setting the OE and OPF pins, the following output enable function can be selected.
In output disable condition, all the outputs take low fixed data or High-Z except for HTPDN, LOCKN and
DGLOCK.
LOCKN
H
L
OE OPF
LVDS Outputs
Status
Output Condition
1
1
0
Output Enable
Low Fixed Data
Hi-Z
0
1
0
Output Disable
Low Fixed Data
Hi-Z
1
1
0
Output Enable
Normal Data
0
1
0
Output Disable
Low Fixed Data
Hi-Z
Table 7. LVDS Output Enable Function
LVDS Data Mapping
LVDS data (video data, control data, DE) are mapped as Figure 9. RLC[6] is special bit for DE (data enable).
RLC[5:4] are for control data bits, and the other bits are for video data. Also there are special assigned bits,
CTLtransmitted under DE=0 condition.
The number of LVDS channels depends on color depth mode, COL.
RLD[6] is not available at COL=0, 8-bit color depth mode.
(RLCLKzp) (RLCLKzn)
Vdiff = 0
tRCOP
Data width
32 24
Previous cycle
Current cycle
Next cycle
RLAzp/n
RLAz[1] RLAz[0] RLAz[6] RLAz[5] RLAz[4] RLAz[3] RLAz[2] RLAz[1] RLAz[0] RLAz[6] RLAz[5] RLAz[4] RLAz[3] RLAz[2] RLAz[1] RLAz[0]
RLBzp/n
RLBz[1] RLBz[0] RLBz[6] RLBz[5] RLBz[4] RLBz[3] RLBz[2] RLBz[1] RLBz[0] RLBz[6] RLBz[5] RLBz[4] RLBz[3] RLBz[2] RLBz[1] RLBz[0]
RLCzp/n
RLDzp/n
RLCz[1] RLCz[0] RLCz[6] RLCz[5] RLCz[4] RLCz[3] RLCz[2] RLCz[1] RLCz[0] RLCz[6] RLCz[5] RLCz[4] RLCz[3] RLCz[2] RLCz[1] RLCz[0]
(DE) (V)
(H)
(DE) (V)
(H)
RLDz[1] RLDz[0] RLDz[6] RLDz[5] RLDz[4] RLDz[3] RLDz[2] RLDz[1] RLDz[0] RLDz[6] RLDz[5] RLDz[4] RLDz[3] RLDz[2] RLDz[1] RLDz[0]
RLEzp/n
z = 0,1,2,3
RLEz[1] RLEz[0] RLEz[6] RLEz[5] RLEz[4] RLEz[3] RLEz[2] RLEz[1] RLEz[0] RLEz[6] RLEz[5] RLEz[4] RLEz[3] RLEz[2] RLEz[1] RLEz[0]
Data Enable Control Data Bits
Figure 9. LVDS Output Switching Timing Diagram
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