|
|
PDF UPB8214 Data sheet ( Hoja de datos )
| Número de pieza | UPB8214 | |
| Descripción | PRIORITY INTERRUPT CONTROLLER | |
| Fabricantes | NEC | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de UPB8214 (archivo pdf) en la parte inferior de esta página. Total 7 Páginas | ||
|
No Preview Available !
NEe Microcomputers, Inc.
NEC
fL PB8214
PRIORITY INTERRUPT CONTROLLER
DESCRIPTION
The jlPB8214 is an eight-level priority interrupt controller. Designed to simplify
interrupt driven microcomputer systems, the jlPB8214 requires a single +5V power
supply and is packaged in a 24 pin plastic Dual-in-line package.
The jlPB8214 accepts up to eight interrupts, determines which has the highest priority
and then compares that priority with a software created current status register. If the
incoming requires is of a higher priority than the interrupt currently being serviced, an
interrupt request to the processor is generated. Vector information that identifies tl"1 Q
interrupting device is also generated.
The interrupt structure of the microcomputer system can be expanded beyond eight
interrupt levels by cascading jlPB8214s. The jlPB8214's interrupt and vector informa-
tion outputs are open collector and control signals are provided to simplify expansion
of the interrupt structure.
F EATU RES • Eight Priority Levels
• Current Status Register and Priority Comparator
• Easily Expanded Interrupt Structure
• Single +5 Volt Supply
PIN CONFIGURATION B(j
B,
B2
SGS 4
5
ClK 6
INTE
AD 8
Ai 9
IS 10
GND 12
vcc
ECS
22 FG
21 R6
20 R5
j..tPB 19 R4
8214 18 R3
17 R2
16 R,
15 RO
14 ENlG
13 ETlG
Inputs
RO R7
60 , B2
SGS
Ees
INTE
eLK
ELR
ETLG
Outputs
AO--A2
INT
ENLG
PIN NAMES
Request Levels IR7 Highest PnorHyl
Current Status
Status Group Select
Enable Current Status
Interrupt Enable
Clock liNT F·F)
Enable Level Read
Enable ThIs Level Group
Request Levels
JOpen
Interrupt (Act. Low) ~Collector
Enable Next Level Group
II
553
1 page  
ILPB8214
FUNCTIONAL
DESCRIPTION
(CONT.)
RESTART GENERATION TABLE
D7 D6 D5 D4 D3 D2 D, DO
A2 Ai ADPRIORITY
REOUEST
RST
1
1
111
LOWEST R(i 7
111111 1 1
I R1 6
R2 5
11 110 1 1 1
1 1 10 1 1 1 1
R3 4
11 100 1 1 1
R4 3
11011 1 11
115 2
1 10 10 1 1 1
As 1
1 1001 1 1 1
HIGHEST R7
O·
1
1
00
0
1
1
1
'CAUTION RST 0 will vector the program counter to location 0 (zero) and
invoke the same routine as the "RESET" input to SOSOA
Current Status Register
The current status register is designed to prevent an incoming interrupt request from
overriding the servicing of an interrupt with higher priority. Via software, the priority
level of the interrupt being serviced by the microprocessor is written into the current
status register on BO-B2' The bit pattern written should be the complement of the
interrupt level.
The interrupt level currently being serviced is written into the current status register
by driving ECS (Enable Current Status) low. The IlPB8214 will only accept interrupts
with a higher priority than the value contained by the current status register. Note
that the programmer is free to use the current status register for other than as above.
Other levels may be written into it. The comparison may be completely disabled by
driving SGS (Status Group Select) low when ECS is driven low. This will cause the
IlPB8214 to accept incoming interrupts only on the basis of their priority to each
other.
Priority Comparator
The priority comparator circuitry compares the level of the interrupt accepted by the
priority encoder and request latch with the contents of the current status register.
If the incoming request has a priority level higher than that of the current status
register, the INT output is enabled. Note that this comparison can be disabled by
loading the current status register with SGS=O.
Expansion Control Signals
A microcomputer design may often require more than eight different interrupts. The
IlPB8214 is designed so that interrupt system expansion is easily performed via the
use of three signals: ETLG (Enable This Level Group); ENLG (Enable Next Level
Group); and ELR (Enable Level Read). A high input to ETLG indicates that the
IlPB8214 may accept an interrupt. In a typical system, the'ENLG output from one
IlPB8214 is connected to the ETLG input of another IlPB8214, etc. The ETLG of
the IlPB8214 with the highest priority is tied high. This configuration sets up
priority among the cascaded IlPB8214's. The ENLG output will be high for any
device that does not have an interrupt pending, thereby allowing a device with lower
priority to accept interrupts. The ELR input is basically a chip enable and allows
hardware or software to selectively disable/enable individiJaIIlPB8214's. A low on
the ELR input enables the device.
557
5 Page | ||
| Páginas | Total 7 Páginas | |
| PDF Descargar | [ Datasheet UPB8214.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| UPB8212 | 8-Bit Input/Iutput Port |  NEC Electronics |
| UPB8214 | PRIORITY INTERRUPT CONTROLLER | NEC |
| UPB8216 | (UPB8216 / UPB8226) 4-Bit Parallel Bidirectional Bus Drivers | NEC |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |