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Número de pieza | UPD7720 | |
Descripción | DIGITAL SIGNAL PROCESSOR | |
Fabricantes | NEC | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de UPD7720 (archivo pdf) en la parte inferior de esta página. Total 17 Páginas | ||
No Preview Available ! NEt Microcomputers, Inc.
DIGITAL SIGNAL PROCESSOR
NEe
,.,. PD7720
~rn~[~~~ ~illrnW
DESCR IPTION
The NEC pPD7720 Signal Processing Interface (SPI) is an advanced architecture
microcomputer optimized for signal processing algorithms. Its speed and flexibility
allow the SPI to efficiently implement signal processing functions in a wide range of
environments and applications.
The NEC SPI is the state of the art in signal processing today, and for the future.
APPLICATIONS
• Speech Synthesis and Analysis
• Digital Filtering
• Fast Fourier Transforms (FFT)
• Dual·Tone Multi·Frequency (DTMF) Transmitters/Receivers
• High Speed Data Modems
• Equalizers
• Adaptive Control
• Sonar/Radar Image Processing
• Numerical Processing
PERFORMANCE
BENCHMARKS
• Second Order Digital Filter (BiQuad)
• SINE/COS of Angles
• p/A LAW to Linear Conversion
• FFT: 32 Point Complex
64 Point Complex
2.25ps
5.25ps
0.50 ps
0.7 ms
1.6 ms
FEATURES
• Fast Instruction Execution - 250 ns
• 16 Bit Data Word
• Multi-Operation Instructions for Optimizing Program Execution
• Large Memory Capacities
- Program ROM
- Coefficient ROM
512 x 23 Bits
510 x 13 Bits
- Data RAM
128x16Bits
• Fast (250 ns) 16 x 16-31 Bit Multiplier
• Dual Accumulators
• Four Level Subroutine Stack for Program Efficiency
• Multiple I/O Capabilities
- Serial
- Parallel
- DMA
• Compatible with Most Microprocessors, Including:
- pPD8080
- pPD8085
- pPD8086
- pPD780 (Z80™*)
• Power Supply +5V
• Technology NMOS
• Package - 28 Pin Dip
II
*Z80 is a trademark of Zilog Corporation.
519
1 page Il-PD7720
INPUT/OUTPUT
General
The NEC 5PI has 3 communication ports; 2 serial and one 8-bit parallel, each with
their own control lines for interface handshaking_ The parallel port also includes DMA
control lines (DRQ and DACK) for high speed data transfer and reduced processor
overhead_ A general purpose 2 bit output (see Figure 1) port, rounds out a full comple-
ment of interface capability_
<:
OMA
{
INTERFACE
INTERRUPT
RESET
CLOCK
-:> 00- 07
AD
WR
CS
AO
- - ",P07720
DACK
ORQ
INT
RST
CLK
SO
SORQ
S5Eiii
SCK
SI
SIEN
Po
PI
SERIAL I/O
INTERFACE
} OUTPUT PORT
Serial I/O
Two shift registers (51, 50) that are software-configurable to 8 or 16 bits land are
externally clocked (5CK) provide simple interface between the 5PI and serial periph-
erals such as, A/D and D/A converters, codecs, or other 5Pls_
SERIAL I/O TIMING
SCK
<l>s
SORa
SQEN
OUTPUT
DATA
____~--------~.-----
--~/ ______ ------
HIGH Z
tSORS 140A6 5 OR _(.'_- _--_-__H_IG_H_ Z
.JSO ACK
_SOLOAD~~ _____________________________~,_____L,_________
INPUT OATA __..J'~__...r..---"__J\....__'____.J"___=___"'""""*__...r..-'"8:..,:0:.:.;Rc:;5J'-'-'4-,-O",R.:.;6:J\.-'5";..;0;.;.;Rc;.7J'--__- - ' ' - - _
_~~_--_--_--_--_-_--_--_--_--_--_--_-_--_--_--_-~_I~rI~_____
SI REG
LOAS~:~~E
~
CD Data clocked out on falling edge of SCK.
@ Data clocked in on rising edge of SCK.
@ Broken line denotes consecutive sending of next data.
PARALLEL I/O
The 8-bit parallel I/O port may be used for transferring data or reading the 5PI's
status_ Data transfer is handled through a 16-bit Data Register (DR) that is software-
configurable for double or single byte data transfers_ The port is ideally suited for
operating with 8080,8085 and 8086 processor buses and may be used with other
processors and computer systems_
523
5 Page j.tPD7720
Table 10. Condition Field Specifications
BRCH/CNO Fields
Mnemonic 020 019 018 017 016 015 014 013
Conditions
JMP
CALL
JNCA
JCA
JNCB
JCB
JNZA
JZA
JNZB
JZB
JNOVAO
JOVAO
JNOVBO
JOVBO
JNOVAl
JOVAl
JNOVBl
JOVBl
JNSAO
JSAO
JNSBO
JSBO
JNSAl
JSAl
JNSBl
JSBl
JDPLO
JOPLF
JNSIAK
JSIAK
JNSOAK
JSOAK
JNROM
JROM
10 0
10 1
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 10
0 0 0 0 0 No Condition
0 0 0 0 0 No Condition
0 0 0 0 0 CA= 0
0 0 0 0 1 CA= 1
0 0 0 1 0 CB = 0
0 0 0 .1 1 CB = 1
0 0 1 0 0 ZA=O
0 0 1 0 1 ZA= 1
0 0 1 1 0 ZB = 0
0 0 1 1 1 ZB = 1
0 1 0 0 0 OVAO= 0
0 1 0 0 1 OVAO= 1
0 1 0 1 0 OVBO= 0
0 1 0 1 1 . OVBO = 1
0 1 1 0 0 OVAl =0
0 1 1 0 1 OVAl = 1
0 1 1 1 0 OVBl = 0
0 1 1 1 1 OVBl = 1
1 0 0 0 0 SAO=O
1 0 0 0 1 SAO = 1
1 0 0 1 0 SBO= 0
1 0 0 1 1 SBO = 1
1 0 1 0 0 SAl = 0
1 0 1 0 1 SAl = 1
1 0 1 1 0 SBl = 0
1 0 1 1 1 SBl = 1
1 1 0 0 0 DPL = 0
l' 1 0 0 1 DPL = F (HEX)
1 1 0 1 0 SI ACK = 0
1 1 0 1 1 SI ACK = 1
1 1 1 0 0 SO ACK = 0
1 1 1 0 1 SO ACK = 1
1 1 1 1 0 ROM=O
1 1 1 1 1 ROM = 1
*BRCH or CND values not in this table are prohibited.
529
11 Page |
Páginas | Total 17 Páginas | |
PDF Descargar | [ Datasheet UPD7720.PDF ] |
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