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PDF UPD72012 Data sheet ( Hoja de datos )

Número de pieza UPD72012
Descripción HUB CONTROLLER
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DATA SHEET
MOS INTEGRATED CIRCUIT
µPD72012
HUB CONTROLLER FOR UNIVERSAL SERIAL BUS
The µPD72012 is a dedicated LSI for a HUB connected to a universal serial bus (USB) system.
It is an upgrade of NEC’s µPD72011. It complies with USB specification revision 1.1.
By putting descriptors into ROM, information such as a user’s vendor ID can be implemented in the chip.
FEATURES
{ Compliant with Chapter 11 (HUB Specifications) of USB Specification 1.1.
{ Descriptors into ROM
The user can customize the vendor ID and product ID by using Mask ROM option.
{ Supports 5 kinds of string descriptors (for Mask ROM code product only)
{ On-chip sequencer
There is an on-chip descriptor and request response sequencer. External initial setup and control is not needed
and HUB functions can be realized using only the µPD72012.
{ Downstream ports
Four or five ports can be selected using a pin function.
{ Power modes
Bus power or self-power can be selected using a pin function (an external power control circuit is required).
{ Corresponds to standard descriptor products
Two kinds of standard ROM code products are provided. Standard and HUB class descriptors are on-chip in
the µPD72012.
ROM code: 003 (individual overcurrent monitoring type Generic HUB)
ROM code: 004 (collective overcurrent monitoring type Generic HUB)
{ Supports two kinds of clock input
48 MHz oscillator input or a 4 MHz crystal resonator can be supported
{ Power control
Port power control and overcurrent detection functions are on-chip. Individual port control or collective control
can be selected for these.
ORDERING INFORMATION
Part No.
µPD72012CU-XXX
µPD72012GB-XXX-3B4
Package
42-pin plastic SDIP (15.24 mm (600))
44-pin plastic QFP (10 × 10)
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. S13918EJ3V0DS00 (3rd edition)
Date Published April 2001 NS CP(K)
Printed in Japan
The mark shows major revised points.
1999

1 page




UPD72012 pdf
PIN NAME
AGND1
AGND2
AVDD1
AVDD2
CLKSEL
CLK/X2
CS1
CS2
CS3
CS4
CS5
D10
D11
D20
D21
D30
D31
D40
µPD72012
: Analog GND1 (Xtal)
: Analog GND2 (DPLL)
: Analog VDD1 (Xtal)
: Analog VDD2 (DPLL)
: Clock Frequency Control
: 48 MHz OSC, 4 MHz Xtal
Clock Input
: Over Current Detect #1
: Over Current Detect #2
: Over Current Detect #3
: Over Current Detect #4
: Over Current Detect #5
: Downstream Port #1 D+
: Downstream Port #1 D–
: Downstream Port #2 D+
: Downstream Port #2 D–
: Downstream Port #3 D+
: Downstream Port #3 D–
: Downstream Port #4 D+
D41
D50
D51
DGND
DGND (Buffer)
DVDD
DVDD (Buffer)
OSL
PP1
PP2
PP3
PP4
PP5
PSSEL
PVSEL
RST
UD0
UD1
X1
: Downstream Port #4 D–
: Downstream Port #5 D+
: Downstream Port #5 D–
: Digital GND
: Digital GND (Buffer)
: Digital VDD
: Digital VDD (Buffer)
: OSC Suspend Output
: Port Power Control #1
: Port Power Control #2
: Port Power Control #3
: Port Power Control #4
: Port Power Control #5
: Powered Mode Control
: Down Port Value Control
: Reset
: Root Port #0 D+
: Root Port #0 D–
: 4 MHz Xtal Clock Input
Data Sheet S13918EJ3V0DS
5

5 Page





UPD72012 arduino
1.3 Equivalent Circuits of Pins
Type
5 V tolerant
input pin
(Schmitt)
Equivalent Circuit
µPD72012
Pins
RST, CS1 to CS5
Function
3.3 V Schmitt input pin with 5 V tolerant.
5 V tolerant
input pin
5 V Schmitt on-chip
CLKSEL, PSSEL,
PVSEL
3.3 V input pin with 5 V tolerant.
5 V tolerant
clock input
pin
5V
5 V tolerant
3.3 V output
pin
5V
Open-drain
output pin
3.3 V, IOL=6 mA
X1, CLK/X2
3.3 V dedicated clock input pin with 5 V
tolerant.
OSL
3.3 V output pin with 5 V tolerant.
Pull-up to 5 V line is possible.
PP1 to PP5
Open-drain structure pin.
USB buffer
IN/OUT(D+)
(D)
RxDATA
UD0, UD1, D10 to
D50, D11 to D51
RxSE0
TxDATA
USB buffer. The two kinds of receiver are
DATA receiver and SE0 (single end 0) receiver
on the receiving side.
On the sending side, rise and fall times are
managed in the last stage of the buffer in
order to create a difference between low-speed
and full-speed.
Data Sheet S13918EJ3V0DS
11

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