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PDF MA009A Data sheet ( Hoja de datos )
| Número de pieza | MA009A | |
| Descripción | 24-Bit I/O Extender | |
| Fabricantes | Megawin | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de MA009A (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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MA009A
24-bit I/O extender with interrupt function
Features
• Operation voltage: 2.0V to 5.7V
• Low standby current (1uA, typ.)
• 2 Mbps, 3-wire serial interface
• 8 chip addresses are provided
• 24 input/output pins
Selection Information
Package / Dice
Parallel Input
Parallel Output
Parallel I/O
Max. Sink Current
MA009AH
Dice
Application Field
System I/O port
LED status indicator
♦ 16 input pins with pull-high disable/enable
and interrupt function
♦ 16 output pins with CMOS/NMOS,
large/small sink capability
MA009AP
44-PLCC
8 pins
8 pins
8 pins
20mA
MA009AD
48-LQFP
MA009AF
44-PQFP
This document contains information on a new product under development by MEGAWIN. MEGAWIN reserves the right to change or discontinue
this product without notice.
© MEGAWIN Technology Co., Ltd. 2006 All rights reserved.
2006/09 version A1
MEGAWIN
1 page  
Control Registers Definition
The default value of all the control register is 0 after power on.
Chip Address
Name
C_ADDR
Bit 7
-
Chip address register.
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
A02
Bit 1
A01
Bit 0
A00
Only the contents of chip address register are same as chip address pin A2, A1 and A0, all command could be
enabled. This function will make the master to connect more than one MA009 easily.
Input Port 0
Name
Bit 7 Bit 6
P0 P07 P06
Port P0 input status register.
Bit 5
P05
Bit 4
P04
Bit 3
P03
Bit 2
P02
Bit 1
P01
Bit 0
P00
Name
P0PR
Bit 7
-
Bit 6
-
Port P0 pull high control register.
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2 Bit 1 Bit 0
- PR01 PR00
P0PR.0: P0.0 ~ P0.3 pull high control, 0: enable (large resistance, 350K), 1: disable
P0PR.1: P0.4 ~ P0.7 pull high control, 0: enable (large resistance, 350K), 1: disable
Name
Bit 7 Bit 6 Bit 5
P0PSR - - -
Port P0 strong pull high selection register.
Bit 4
-
Bit 3
-
Bit 2 Bit 1 Bit 0
- PS01 PS00
P0PSR.0: P0.0 ~ P0.3 strong pull high selection, 0: disable, 1: enable (small resistance, 50K)
P0PSR.1: P0.4 ~ P0.7 strong pull high selection, 0: disable, 1: enable (small resistance, 50K)
Name
P0IEN
Bit 7
IE07
Bit 6
IE06
Port P0 interrupts enable register.
Bit 5
IE05
Bit 4
IE04
Bit 3
IE03
Bit 2
IE02
Bit 1
IE01
Bit 0
IE00
P0IEN.0 ~ P0IEN.7: P0.0 ~ P0.7 falling edge interrupts control, 0: disable, 1: enable
Name
P0EVT
Bit 7 Bit 6 Bit 5
ST07 ST06 ST05
Port P0 interrupts events status register.
Bit 4
ST04
Bit 3
ST03
Bit 2
ST02
Bit 1
ST01
Bit 0
ST00
When a falling edge signal is occurs in any interrupt enabled (the bit 0 or bit 1 of P0IEN is set to 1) pins of port P0,
the corresponding bit of P0EVT will be set to 1. The interrupt will be generated from the INTB (1!0) pin in this
condition, and the mater (for example, a microcontroller) can read the interrupt status from P0EVT. The master
can send EVTCLR (13H) command to MA009 to clear the P0EVT after the interrupt event is processed. This
MEGAWIN
MA009A Technical Summary
5
5 Page 
Pad Assignment
NC
A0
A1
A2
C/DB
SCLK
Sin
NC
NC
1
2
3
4
5
6
7
8
9
(0,0)
41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
MEGAWIN
MA009A Technical Summary
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet MA009A.PDF ] | |
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