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Número de pieza | UPD8085A-2 | |
Descripción | Single Chip 8-BIT N-CHANNEL MICROPROCESSOR | |
Fabricantes | NEC | |
Logotipo | ||
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fLPD8085A SINGLE CHIP 8·BIT
N·CHANNEL MICROPROCESSOR
NEe
JLPD8085A
JLPD8085A-2
DESC RIPT ION
The j.LPD8085A is a single chip B-bit microprocessor which is 100 percent software
compatible with the industry standard 8080A_ It has the ability of increasing system
performance of the industry standard 8080A by operating at a higher speed. Using
the j.LPD80B5A in conjunction with its family of ICs allows the designer complete
flexibility with minimum chip count.
FEATURES
• Single Power Supply: +5Volt,±10%
• Internal Clock Generation and
System Control
• Internal Serial In/Out Port.
• Fully TTL Compatible
• Internal 4-Level Interrupt Structure
• Multiplexed Address/Data Bus for
Increased System Performance
• Complete Family of Components for
Design Flexibility
• Software Compatible with Industry Standard 8080A
• Higher Throughput: j.LPD8085A - 3 MHz
j.LPD80B5A-2 - 5 MHz
• Available in Either Plastic or Ceramic Package
PIN CONFIGURATION
Xl
X2
RO
SOD
SID
TRAP
RST 7.5
RST 6.5
RST 5.5
INTR
INTA
ADO
ADl
AD2
AD3
AD4
AD5
ADS
AD7
VSS
"PO
8085A
Vee
HOLD
HLDA
eLK lOUT)
RESET IN
READY
loiM
Sl
RD
WR
ALE
So
A15
A14
A13
A12
All
AlO
Ag
AS
REV/2
EI
397
1 page TIMING WAVEFORMS
(CaNT.)
T1
ClK
WRITE OPERATION
TWAIT
,.,.PD8085A
T1
ALE
WR--r---t---~~~-+-------
READY
HOLD OPERATION
ClK
HOlD+_ _ _.IJ
H l D A +_ _ _ _ _ _ _ _ _ _~------~~_.u
INTERRUPT TIMING
T1
II
'HABE~~+-_ _ _ _ _ __ _ _
.-I+-:t-_r.,... 'HDH
JHlDA-----~t~H-A-C-K==1,
tHAlF
~~~-
,~--- _
No'e:G)IO/iiii is also floating during this ti.....
401
5 Page p.PD8085A
INSTRUCTION CYCLE
TIMES
One to five machine cycles (Ml - M5) are required to execute an instruction. Each
machine cycle involves the transfer of an instruction or data byte into the processor or
a transfer of a data byte out of the processor (the sole exception being the double add
instruction). The first one, two or three machine cycles obtain the instruction from the
memory or an interrupting I/O controller. The remaining cycles are used to execute the
instruction. Each machine cycle requires from three to five clock times (Tl - T5).
Machine cycles and clock states used for each type of instruction are shown below.
INSTRUCTION
TYPE
ALU R
CMC
CMA
DAA
DCR R
DI
EI
INR R
MOV R, R
NOP
ROTATE
RIM
SIM
STC
XCHG
HLT
DCX
INX
PCHL
RETCOND.
SPHL
ALU I
ALU M
JNC
LDAX
MVI
MOV M, R
MOV R, M
STAX
CALL CONDo
DAD
DCR M
IN
INR M
JMP
LOAD PAIR
MVIM
OUT
POP
RET
PUSH
RST
LDA
STA
LHLD
SHLD
XTHL
CALL
MACHINE CYCLES EXECUTED
MIN/MAX
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1/3
1
2
2
2/3
2
2
2
2
2
2/5
3
3
3
3
3
3
3
3
3
3
3
3
4
4
5
5
5
5
CLOCK STATUS
MIN/MAX
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
5
6
6
6
6/12
6
7
7
7/10
7
7
7
7
7
9/18
10
10
10
10
10
10
10
10
10
10
12
12
13
13
16
16
16
18
II
407
11 Page |
Páginas | Total 13 Páginas | |
PDF Descargar | [ Datasheet UPD8085A-2.PDF ] |
Número de pieza | Descripción | Fabricantes |
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