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PDF UPD8080AF-1 Data sheet ( Hoja de datos )

Número de pieza UPD8080AF-1
Descripción 8-BIT N-CHANNEL MICROPROCESSOR
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD8080AF-1 Hoja de datos, Descripción, Manual

NEe Microcomputers, Inc.
JLPD8080AF 8-BIT N-CHANNEL
MICROPROCESSOR FAMILY
NEe
fLPD8080AF
fL PD8080AF·2
fL PD8080AF·1
DESCRIPTION
FEATURES
The IlPD8080AF is a complete 8-bit parallel processor for use ill general purpose
digital computer systems_ It is fabricated on a single LSI chip using N-channel silicon
gate MOS process, which offers much higher performance than conventional micro-
processors (1.28Ils minimum instruction cycle). A complete microcomputer system
is formed when the IlPD8080AF is interfaced with I/O ports (up to 256 input and 256
output ports) and any type or speed of semiconductor memory. It is available in a
40 pin ceramic or plastic package.
78 Powerful Instructions
• Three Devices - Three Clock Frequencies
pPD8080AF - 2.0 MHz
IlPD8080AF-2 - 2.5 MHz
uPD8080AF-l - 3.0 MHz
• Direct Access to 64K Bytes of Memory with 16-Bit Program Counter
• 256 8-Bit I nput Ports and 256 8-Bit Output Ports
• Double Length Operations Including Addition
• Automatic Stack Memory Operation with 16-Bit Stack Pointer
• TTL Compatible (Except Clocks)
• Multi-byte Interrupt Capability
• Fully Compatible with Industry Standard 8080A
• Available in either Plastic or Ceramic Package
PIN CONFIGURATION
AlO
VSS
D4
D5
D6
D7
D3
D2
Dl
DO
VBB
RESET
HOLD
INT
<1>2
INTE
DBIN
WR
SYNC
VCC
1
2
3
4
5
6
7
S
9
10
,",PO
118080AF
12
13
14 27
15
16 25
17
18
19
20 21
All
A14
A13
A12
A15
A9
AS
A7
A6
A5
A4
A3
VDD
A2
AI
AO
WAIT
READY
<1>1
HLDA
II
Rev/l
383

1 page




UPD8080AF-1 pdf
AC CHARACTERISTICS
fJPD8080AF
~PD8080AF
Ta '" aOc to +70°C, Voo = +12V ± 5%, Vee = +SV ± 5%, Vss = -5V ± 5%, Vss = av, unless otherwise
specified.
PARAMETER
SYMBOL
LIMITS
MIN TYP MAX
UNIT
TEST CONOITIONS
Clock Period
Clock Rise and Fall Time
¢1 Pulse Width
4>2 Pulse Width
Delay </>1 '0 </>2
Delay q,2 to 4>1
Delay 4>1 to </)2 Leading Edges
Address Output Delay From ¢2
Data Output Delay From 11>2
Signal Output Delay From ¢1,
or <1>2 (SYNC, WR. WAIT,
HLOAI
DBIN Delay From t:/>2
Delay for I nput Bus to Enter
Input Mode
Data Setup Time During 4>1 and
OSIN
Data Setup Time to ¢2 During
OBIN
Data Hold Time From ¢2 During
CSIN
INTE Output Delay From ct>2
READY Setup Time During cP2
HOLD Setup Time to ¢2
tNT Setup Time During ¢2
(During $1 in Halt Mode)
Hold Time from 4>2 (READY,
INT, HOLOI
Delay to Float DUring Hold
(Address and Data Bus)
Address Stable Prior to WR
Output Data Stable Prior to WR
Output Data Stable From WR
Address Stable from WR
HLDA to Float Delay
WR to Float Delay
Address Hold Time after DBIN
during HLDA
'CY@
tr,tf
'</>1
'</>2
'01
'02
'03
'OA@
'OD@
O.4S
0
60
220
0
70
SO
'OC@
'OF@
'01 CD
25
'OSl
'OS2
'OH CD
'IE ®
'RS
'HS
30
150
CD
120
140
'IS 120
'H 0
'FO
'AW@
'OW@
'WO®
'WA®
'HF ®
'WF ®
'AH ®
®
®
C!.
C!.
@:
(9
-20
2.0 ,usee
50 nsec
nsec
nsec
nsec
nsec
nsec
200 nsec
CL"l00pF
220 osec
120 nsec CL" 50 pF
140 nsec
'OF nsec
nsee
nsec
nsec
200 nsec CL - 50 pF
nsec
nsec
nsec
nsec
120 nsec
nsec
nsec
nsec
nsec
CL " 100 pF: Address,
Data
nsec
nsec
CL "50 pF: WR.
HLOA,OBIN
nsec
<DNotes:
Data input should be enabled with DBIN status, No bus conflict can then occur and data hold time
is assured. tOH """ 50 ns or tDF. whichever is less,
@ Load Circuit.
+5V
I I2.1K
MP08080AFo-__. -____. -__-i(~--_+
OUTPUT
@ Ac,ual 'eY "'03 + 'r<l>2 + '<1>2 + 'f<l>2 + '02 + 'r</>l > 'CY Min.
TYPICAL f). OUTPUT DELAY VS.
f). CAPACITANCE
+20
!
/
> +10
~
'.0".. 0
.i.'.
/
/ ......... SPEC
" /-10
0
<l
-20
-100
-50
o
+50
a CAPACITANCE (pH
(CACTUAL - CSPEcl
+100
387

5 Page





UPD8080AF-1 arduino
INSTRUCTION SET TABLE
MNEMONIC'
DESCRIPTION
INSTRUCTION CODE 2
07 06 Os 04 03 02 0, DO
eloele
eve.as3
.FLAGS4
>
*~ ~
MOVE
MNEMONIC'
DESCRIPTION
MOV,' ,
MVI M,D8
Mov~ 'eql'lP' 10 rpq1'1~r
Moveregtswr wrT1emory
Move memory to req,ster
Move Immed,a!e to ,e9"le,
Move ,mmedl,l1e to memory
o,
dn
10
" ,' 00
l;XI8,016
LXI 0,016
LXI H,D16
LOdO immed"l1e ,eq's!",
p,'" Be
load ,mmed,ale reg"'er
pair DE
Load Immed',l1e ,eqlSlel
INCREMENT "DECREMENT
'flcremenlreg,ste r
Dec.emefll reqlster
" "d
o0
o,
tocrementmemo,y
o o0
Decrement memory
o,
r-___________________-_R_'G~'_ST_'_R_TO~A~C~CU~M~U~L_AT~O_R________________~ PUSHD
ANA s
XRA s
Add '''!l,S(er to A
Add r~q,\!er 10 A ",,[1\
ca"y
,
Subtract ,,,glster from A
Subtract ,eglsTe, t'om A
AND reg'Sle, "'t!h A
e,cluslve OR Reg'11e,
with A
OR req"le' w"h A
Compdre ,eglsler w,lh A
,0
, 00
,
1a 10
o,
,, 0
PUSH H
o POP B
POP D
Po,m/!,
Push reglSl!!r Pdlr BC
Push reg'SI!!r p~" DE
Push reg,stel pair HL
Push A and fla~. on slack
Pop regtster pair BC all
Pop reg,sTer palf DE off
Pop register pair HL off
ILPD8080AF
INSTRUCTION CODE 2
Clock
07 06 Os 04 03 02 0, DO eye'lsl
LOAD REGISTER PAIR
0000000
o0 1 1 0 0 0
PUSH
10 0 10
,0,
eo,
""
o10 aa 1
ADC M
ORA M
AOI DB
SBID8
ORI DB
MEMORY TO ACCUMULATOR
Add memory 10 A
Add memory to A wllh
Cdrry
Subtract memory from A
Subtract memory from A
AND memory With A
Exclus've OR memory
wllh A
OR memory wllh A
Comp"'e memory With A
,
o,
,
o0
'0
,0
,0
,0
,0
IMMEDIATE TO ACCUMULATOR
Add Immed'~le 10 A
10 0 0 1 10
Add Immed,ale 10 A wllh
'0
,
Subtract ,mmedla1e tram A 1
0 10 1
SUblldC1lmmed'dle from A
AND Immediate With A
'0
,
a1
E~clus've OR Immediate
,0
OR Immed,ate wllh A
Compare Immediate w'Ih A
ROTATE
Rotate A lefl, MSB to
carrl'lB_blll
Rotate A ri9h1, LSB 10
ca"v IB-bltl
Rotate A leflthrough
carry IS-bill
Rotate A fIght Through
CaffY IS-b'tl
o0 0 0 1
o0 0 1
POP PSW
Pop A and flags off Slack
DOUBLE ADO
PAD B
DADSP
Add BC to HL
Add DE to HL
Add Stack Po,nter !O Hl
0000100
oa 0 1
a0 1a1
o0 ,
INCREMENT REGISTER PAIR
INX B
INX 0
Incremem DE
Increment HL
Increment Stack Poonter
0000001
aaa10 0 1
0010001
o0
DCX 0
DCX H
I)CX SP
DECREMENT REGISTER PAIR
Oecremem BC
Decrement Stack POln!er
,0 0 0 0 1 0
o
aa 10
o
o0 ,
,0
,
,
REGISTER INDIRECT
STAX B
STAX 0
Store A ~t ADDR on BC
Slore A at AD DR In DE
Load A at ADDR tn BC
Load A at ADDR ,n DE
00000010
o0 0
o0
o0 0
,0
,0,
STA ADDR
LOA ADOR
SHLD AODR
Store A direct
Load A direct
Store HL dtrect
Load, Hl dlrec1
DIRECT
o 10 0
o0 1
10
1 0 0I0
1a1a
1
1
MOVE REGISTER PAIR
XCHG
Exchange DE and HL
'6
JNZ 'ADDR
JZ ADDR
JNC ADDR
JC ADDR
JP ADDR
JM AODR
Jump uncond'tlonal
Jump on not ~ero
Jump On zero
Jump On nO carry
Jump on carry
Jump on parity odd
Jump On parl1y even
Jump on Posl!lve
Jump On minus
o0 a0 1 1
000010
o0 1 0 10
o10 0 10
o1 10
1aa0
o10 10
10 0 10
o
CALL
SPHL
'N A
OUT A
"
RST A
Exchange top of stack
and HL
HL!o Stack Po,nter
HL to Program Counter
froput
Output
Enable Interrupts
DlSable,nterrupT ..
100
,
,0
1
01
INPUT/OUTPUT
1a
o
01
0
o
o,
"5
5
CZ ADOR
CNC ADDR
CC ADOR
CPO ADDR
CPE ADDR
Call uncond,t,oroal
Call on not zero
Call on ~ero
Callan nO carry
Call On carry
Call on parl!y odd
Callan panty eV!!n
Callan POiltlV!!
o0 ,
o,
10 0 0
a0
10 a
o1
10 0
10 1
10 a
o0 10 0
a 1 1 a0
10
a0
11/17
11/17
11117
11117
11/17
11/17
STC
DAA
NO'
HeT
Complement A
Set carry
Complement carry
Decimal adJust A
No operation
Halt
MISCELLANEOUS
o, ,
,0,
o0 ,
o0
oa
o1
00
10
1C-M-AD-D-R-------------------------------------11-11-7---------1 NOTes
I -______________________R_'_TU_R_N________________________- I 10peran~ ~y::,~I:~;~:~s or expreSSion
2~~~ :r_sslsl~ ~Oe~~r~~; 1~ ~.010 a - 011 E - 100 H -
RZ
RNC
RC
RR'O"
R'
RM
Return On not zero
Return on uro
Return on no carry
Return on carr,;
Return on p~"ty odd
Return onparoty even
Return on poso!lve
Returro on monu5
o0
10 0
0a1
aa
10 0 1
00
o10 0 0 0
10
o1
o
10 a
5111
5111
5111
5111
5111
5,11
5/11
51,1
~ = SOurce regisTel
d ~ deSTinaTioro register
PSW ~ ProceSSOr STaTu~ Word
SP ~ Stack Poonter
08 ~ B-b,t daTa quanli!,;, e.p,esSlon, or
constant, always B2 of on5Truct,on
016 - lS-b,T data quantity, el(pre~5;on, Or
conStant, always 83B2 of instrucT,on
ADOR - lS-b,t"Memory address expression
lTwo possible cycle times IS/II) ond'cate
instrllction cycles dependenT on cond,noro
!tags,
4. _ flag af1ecled
_ flag nOT affected
a - flag reset
I = flag .et
,
C;
II
393

11 Page







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