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PDF UPD8041 Data sheet ( Hoja de datos )
| Número de pieza | UPD8041 | |
| Descripción | UNIVERSAL PROGRAMMABLE PERIPHERAL INTERFACE - 8-BIT MICROCOMPUTER | |
| Fabricantes | NEC | |
| Logotipo |  |
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NEe Microcomputers, Inc.
ttt{EC
P.PD8041
UNIVERSAL PROGRAMMABLE PERIPHERAL
INTERFACE - 8·BIT MICROCOMPUTER
DESCR IPT ION
The tLPDB041 is a programmable peripheral interface intended for use in a wide range
of microprocessor systems. Functioning as a totally self·sufficient controller, the
tLPDB041 contains an B-bit CPU, 1K x B program memory, 64 x B data memory, I/O
lines, counter/timer, and clock generator in a 40-pin DIP. The bus structure, data regis-
ter, and status register enable easy interface to B04B, BOBOA, or BOB5A based systems.
FEAT U R ES
• Fully Compatible with B04B, BOBOA and B085A Bus Structure
• B-Bit CPU with 1K x B ROM, 64 x B RAM, B-Bit Timer/Counter, 18 I/O Lines
• 4-Bit Status and 8-Bit Data Register for Asynchronous Siave-to-Master Interface
• Interrupt, DMA, or Polled Operation
• Expandable I/O
• Two Interrupts
• 40-Pin Plastic or Ceramic DIP
• Single +5V Supply
PIN CONFIGURATION
TO
X1
x2
RESET
55
cs
EA
RD
AO
WR
SYNC
DO
D1
D2
D3
D4
D5
D6
D7
VSS
tLPD
8041
VCC
T1
P27
P26
P25
P24
Pn
P16
P15
P14
P13
P12
Pll
P10
VDD
PROG
P23
P22
P21
P20
II
315
1 page  
INSTRUCTION SET
fL PD8041
MNEMONIC
ADD A, :: d,Jta
ADD A. Rr
ADDA,@Rr
ADDC A, :; data
AOOC A, Rr
ADr1C A, @ Rr
ANL A, ~ data
ANL A, Rr
ANLA,@Rr
CPL A
CLR A
DAA
DEC A
INC A
ORL A, = data
ORL A, Ar
ORLA,@Rr
Rl A
RlC A
RRC A
SWAP A
XRLA,..-data
XRL A, Rr
XALA,@Rr
DJNZ Rr, addr
Jab addr
JCadd,
JFO addr
JF1 addr
JMP addr
JMPP@A
JNC addr
JNIBF addr
JOBF
FUNCTION
(AI, 1M + data
1M, IA) + IRd
for r = 0 7
(AI ~ IAI + ((Rdl
for r ~ 0 1
(A), (AI t (CI + data
IAI· (AI + (CI + (Rr)
for r 0 7
(AI, IAI 1- (e) + ((RrI)
for r" 0 ,
(AI· IAI AND data
(AI, (AI AND IRri
lor r - 0 7
(AI·- (AI AND (IRrH
for r ~ 0 ,
IAI ~ NOT IAI
tAl· 0
(AI, (AI 1
INSTRUCTiON CODe
fLAGS
DESCRIPTION
07 06 05 04 03 02 01 DQ CYCLES BYTES C AC FO Fl ISF gBF
A M LATOR
Add Immediate the specified Data to the
1
Accumulator.
d7 d6 dS d4 d3 d2 dl dO
Add contents of desIgnated reg,ster to
the Accumulator.
0
Add Ind.rect the contents the data
memory location to the Accumulator
Add Immediate wIth carry the specIfied
0
11
data to the Accumulator
d7 d6 dS d4 d3 d2 dl dO
Add with carry the contents 01 the
desIgnated reg,ster to the Ac<:umulator.
0
Add Indirect with carry the contents of
data memory location to the
Accumulator
LogIcal and spec,f,ed Immediate Data
With Accumulator.
LogIcal and contents of deSIgnated
regIster With Accumulator
11
d7 d6 dS d4 d3 d2 d1
o0
dO
Logical and Indirect the contents 01 data
memory WIth Accumulator
Complement the contents of the
Accumulato,
CLEAR the contents of the Accumulator
DECIMAL ADJUST the contents of the
Accumulator
DECREMENT by 1 the accumulator's
IAI' IAI + 1
Increment by 1 the accumulator's
IAI' IAI OA data
(AI, (AI OR IRr!
for r ~ 0 7
LogIcal OR or speCified ImmedIate data
WIth Accumulator
Logical ORcontents of deSignated
register With Accumulator.
1
d7 d6 dS d4 d3 d2 dl dO
0
(AI· (AI OA (IAr))
for, ~ 0 ,
Log~at OR IndIrect the contents 01 data
memory locatIon With Accumulator
IAN + 11· IANI
IAOI·- IA71
for N - 0 6
(ANt 11~-IANI,N =0
IAOI- ICI
ICI· 1A71
6
Rotate Accumulator left by l-blt Without
Aotate Accumulator left by l·blt through
(ANI .- IAN + 11. N - 0 6 Aotate Accumulator rogh\ by '·b,t
(A71' lAO)
Without carry
(ANI - IAN i 11: N = 0 . 6
(A71' (CI
ICI· IAOI
(A4-71.· (AO' 31
Rotate Accumulator I>ght by '·b,t
through carry
Swap the 24-b'l n,bbles ,n the
Accumulator.
(AI· (AI XOR data
(AI ~- (A) XOR (Rr)
tor r ~ a - 7
Log,cal XOR spe£lf,ed Immediate data
With Accumulator.
Logical XOA contents of des,gnated
reg»te, With Accumulator.
1 10
'1 1
d7 d6 dS d4 d3 d2 dl dO
(AI' (AI XOR ((Rd)
tor, = 0 - 1
Logical XOR Indirect the contents of data 1
memory location w'th Accumulato,
BRANCH
(Rr) +- (Rr) - 1" ~ 0 - 7
If (Rr)" a
(PC 0 - 7) +- addr
De£rement the specll,ed register and
(PC a - 7)'" addr ,f Bb = 1
(PC), (PC) + 2 ,f Bb = a
(PC 0 - 7) ~ addr ,I C ~ 1
(PC)· (PCI + 2 ,f C = 0
Jump to SpeCified address if
Accumulator bit IS set.
Jump to spec,f,ed address ,I caHy flag
b2 bl bO
a7 ~ as 84 a3
32 al
~
o1
~•
~~Q
~~
~
(PC 0 7) ... addr If FO '" 1 Jump to spec,fled address ,f Flag Fa 1$
(PCI ~I(PC) + 2 If FO = 0
a7 a6 as a4 a3 a2, a1 aO
(PC 0 - 71 +- add, If F 1 = 1
(F-C) ,. (PCI + 2 ,f F1 '" 0
Jump to speclf,ed address ,f Flag F 1 +s
set.
~•
10
~~Q
~~
~
(PC 8 - 101'- addr 8 - 10 D'rect Ju_mp to spec,f,ed address Within al0 a9 a8
0 1 0, 0
(PC 0 - 7) ..... addr 0 - 7
the 2K address block.
a7 a6 8S 84 a3 a2 a1 aO
{PC 111 •. DBF
{PC 0 .. 7) ..... ((A)I
Jump Ind+rect to specrf,ed address WIth
(PC 0 - 7) .... addr if C '" a
(PC) +- (PC) + 2 if C '" 1
..With address page.
Jump to specified address if carry flag IS
low.
a7 .. 'S
'3 '2 '1
(PC 0 - 7) .... addr if tBF '" Jump to specified address if input buffer 1
1
1o1
(PC) .... (PC) + 2 If ISF '" 1 lutl flag is low
a7 .. 'S
'3 '2 '1 '0
'.(PC 0 - 7) .... addr jf OBF '" 1 Jump to specified address it output
ooD 1
o
'. ., '"(PC) .... (PC) + 2 if OBF '" a buffer fult flag is set.
87 a6 as '3 '1
.2
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet UPD8041.PDF ] | |
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