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PDF UPD7801 Data sheet ( Hoja de datos )

Número de pieza UPD7801
Descripción HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD7801 Hoja de datos, Descripción, Manual

NEe Microcomputers, Inc.
NEe
,u.PD7801
HIGH END SINGLE CHIP 8-BIT MICROCOMPUTER
WITH 4K ROM
PRODUCT DESCRIPTION
FEATURES
PIN CONFIGURATION
The NEe ,uPD7801 is an advanced 8-bit general purpose single-chip microcomputer fabricated wIth
N-Channel Silicon Gate MOS technology.
The NEe ,uPD7801 is intended to serve a broad spectrum of 8-bit designs ranging from enhanced
single chip applications extending into the multi -chip microprocessor range. All the basic functional
blocks - 4096 x 8 of ROM program memory, 128 x 8 of RAM data memory, 8-bit ALU, 48 1/0
lines, Serial I/O port, 12-bit timer. and clock generator are provided on-chip to enhance stand-alone
applications. Fully compatible with the industry standard 80S0A bus structure, expanded system
operation can be easily implemented using any of the 8080A/SOS5A peripherals and memory
products. Total memory space can be increased to 64K bytes.
The powerful 140 instruction set coupled with 4K bytes of ROM program memory and 128 bytes
of RAM data memory greatly extends the range of single chip microcomputer applications. Five
level vectored interrupt capability combined with a 2 microsecond cycle time enable the ,uPD7801
to compete with multi-chip microprocessor systems with the advantage that most of the suppOrt
functions are on-chip.
NMOS Silicon Gate Technology Requiring +5V Supply
• Complete Sinqle-Chip Microcomputer with On-Chip ROM'~ RAM and 1/0
- 4K Bytes ROM
'
- 128 Bytes RAM
- 48 1/0 Lines
• Internal 12-81t Programmable Timer
• On-Chip 1 MHz Serial Port
• Five Level Vectored, Prioritized Interrupt Structure
~ Serial Port
~ Timer
~ 3 External Interrupts
• Bus Ex-pansion Capabilities
- Fully 8080A Bus Compatible
- 60K Bytes External Memory Address Range
• On-Chip Clock Generator
• Wait State Capability
• Alternate Z80™ Type Register Set
• Powerful 140 Instruction Set
• 8 Address Modes; Including Auto-Increment/Decrement
• Multi-Level Stack Capabilities
• Fast 2 }.lS Cycle Time
• Bus Sharing Capabilities
PE15
<POUT
D B7
DB6
DB5
DB4
DB3
DB2
DBl
DBa
INT2
INTl
INTO
WAIT
MI
WR
REi
PC7
PC6
PC5
PC4
PC3
PC2
PCl
PCO
SCi<
SI
So
RESET
X2
Xl
VSS(OV)
4
5
6
7
8
9
10
11
12
13
14
lS
16
17
JLPD
7801
18 47
19 46
20 45
44
43
42
41
40
39
3a
37
36
35
34
33
Vcc ,'>SII)
PE14
PE13
PE12
PE11
PE1Q
PE 9
PEa
PE7
PE6
PES
PE4
PE3
PE2
PEl
PEo
PB7
PB6
PBS
PB4
PB3
PB2
PBl
Pao
PA7
PA6
PA5
PA4
PA3
PA2
PAl
PAO
1.1
251

1 page




UPD7801 pdf
FUNCTIONAL
DESCRIPTION
(CONT.)
Timer Operation
~PD7801
TO
TIMER BLOCK DIAGRAM
A programmable 12-bit timer is provided on-chip for measuring time intervals, generat-
ing pulses, and general time-related control functions. It is capable of measuring time
intervals from 4 IlS to 16 IlS in duration. The timer consists of a prescaler which
decrements a 12-bit counter at a fixed 4 IlS rate. Count pulses are loaded into the
12-bit down counter through timer register (TMO and TM 1). Count-down operation is
initiated upon extension of the STM instruction when the contents of the down
counter are fully decremented and a borrow operation occurs, an interval interrupt
(INTT) is generated. At the same time, the contents of TMO and TM1 are reloaded
into the down-counter and countdown operation is resumed. Count operation may be
restarted or initialized with the STM instruction. The duration of the timeout may be
altered by loading new contents into the down counter.
The timer flip flop is set by the STM instruction and reset on a countdown operation.
Its output (TO) is available externally and may be used in a single pulse mode or general
external synchronization.
Timer interrupt (I NTT) may be disabled through the interrupt.
Serial Port Operation
II
~"PC,/SAK
" MC3
,
aA
WA, AI>;
SERIAL PORT BLOCK DIAGRAM
255

5 Page





UPD7801 arduino
INSTRUCTION GROUPS
MNEMONIC OPERANDS
NO. CLOCK
BYTES CYCLES
OPERATION
a·BIT DATA TRANSFER
p.PD7801
SKIP
FLAGS
CONDITION CY Z
MOV
rl,A
1 4 r1-A
MeV
A,rl
1 4 A-r1
Mev
MOV
sr,A
A,srl
2 10 sr-A
2 10 A-sr1
Mev
r, word
4 17 r-(word)
MOV
MVI
MVIW
MVIX
STAW
LDAW
STAX
word, r
r, byte
wa, byte
rPal, byte
wa
wa
rpa
4
2
3
2
2
2
1
17 (word) -r
7 r -byte
13 lv, wei - byte
10 Irpall - byte
10 IV,wal-A
10 A-IV,wal
7 Irpal-A
LDAX
EXX
rPa
1 7 A-Irpal
1 4 Exchange register sets
EX 1 4 V,A"V,A
BLOCK
SBCD
SDED
word
word
1 131C+1I IDEI+ - H!lLI+, C - C - 1
16·BIT DATA TRANSFER
4 20 Iwordl - C, Iword + 11 - B
4 20 Iwordl- E, Iword + 11- D
II
SHLD
word
4 20 Iwordl - L, Iword + 11 - H
SSPD
word
4 20 (wordl- SPL, (word + 11- SPH
LBCD
word
4 20 C - Iwordl, B - (word + 11
LDED
word
4 20 E - Iwordl, D -Iword + 11
LHLD
word
4 20 L - (word I, H - (word + 11
LSPD
word
4 20 SPL - Iword!, SPH - Iword + 11
PUSH
rpl
2 17 (SP - 1.1 - rpl H, ISP - 21 - rpl L
POP rpl
2
15
rpl L -ISPI
rp~-ISP + II, SP-SP + 2
LXI
rp,word
3
10 rp+-word
TABLE
1 19 C- (PC + 2 + AI
B-IPC+2+A+ll
261

11 Page







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