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PDF UPD2147 Data sheet ( Hoja de datos )
| Número de pieza | UPD2147 | |
| Descripción | 4096 x 1 BIT STATIC RAMI | |
| Fabricantes | NEC | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de UPD2147 (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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NEe Microcomputers, Inc.
4096 x 1 BIT STATIC RAMI
NEe
J.L PD2147-2
p.PD2147-3
J.L PD2147-5
FEATURES
The IlPD2147 is a 4096-bit static Random Access Memory organized as 4096 words by
1-bit. Using a scaled NMOS technology, it incorporates an innovative design approach
which provides the ease-of-use features associated with non-clocked static memories
and the reduced standby power dissipation associated with clocked static memories.
The result is low standby power dissipation without the need for clocks, address setup
and hold times. In addition, data rates are not reduced due to cycle times that are
longer than access times.
CS controls the power down feature. In less than a cycle time after CS goes high -
deselecting the IlPD2147 - the part automatically reduces its power requireme"ts and
remains in this lower power standby mode as long as CS remains high. This del/ice
feature results in system power savings as great as 85"10 in larger systems, where the
majority of devices are deselected.
The IlPD2147 is placed in an 18-pin ceramic package configured with the industry
standard pinout. It is directly TTL compatible in all respects: inputs, outputs, and a
single +5V supply. The data is read out non-destructively and has the same polarity
as the input data. A data input and a separate three-state output are used.
• Scaled NMOS Technology
• Completely Static Memory - No Clock or Timing Strobe Required
• Equal Access and Cycle Times
• Single +5V Supply
• Automatic Power-Down
• High Density 18-Pin Package
• Directly TTL Compatible - All Inputs and Outputs
• Separate Data Input and Output
• Th ree-State Output
• Available in a Standard 18-Pin Ceramic Package
• 2 Performance Ranges:
II
I'PD2l47-2
I'PD2l47-3
I'PD2147-5
MAX
ACCESS TIME
70 ns
55 ns
45 ns
SUPPLY CURRENT
ACTIVE
STANDBY
160mA
20 mA
160 mA
20mA
leO mA
20 mA
PIN CONFIGURATION
AO
A,
A2
A3
A4
A5
DOUT
WE
GND
Vec
Ae
A7
AS
Ag
AlO
All
.DIN
CS
PIN NAMES
AO-All
WE
CS
DiN
DOUT
Vee
GND
Address Inputs
Write Enable
Chip Select
Data Input
Data- Output
~ower (+5V)
Ground
TRUTH TABLE
cs WE
MODE
OUTPUT
H X Not Selected High Z
L L Write
High Z
L H Read
DOUT
POWER
Standby
Active
Active
65
1 page  
TIMING WAVEFORMS
WRITE CYCLE
f'PD2147
WRITE CYCLE NO.1 (WE CONTROLLED) @
ADDRESS
'wc
bJ,..
\'
'CW
II IIII
r-----'AS
WE
'AW
r - - - twP -
-\:\
-'WR-
t: -'DW
~tDH
DATA IN
DATA IN VALID
* t--'WZ
-'DW
--------____=,......----?DATADUT ______~D~A:T~A~U~N~D~EF~I~N~E~D~____~-l-HtIG_H -IM--P-E-D-A~N~C.--:1-.-.------
II
WRITE CYCLE NO.2 (Cs CONTROLLED) @
'wc
ADDRESS
tAS-
- -i
'cw
'AW _
<-
'WP_ _'WR_
.t. *\\\\\\\\\\
IIIIIII
-'DW
'D~t.
DATA IN
DATA IN VALID
________----------:-1DATA OUT
DATA UNDEFINED
I--'wz
:=)t--H-------IGH IMPEDANCE ----
CDNotes;
IfCS goes high simultaneously with WE high, the output remains in a high impedance
state.
® All Write Cycle timings are referenced from the last valid address to the first
transitioning address.
@ Transition is measured at VOL +200 mV and VOH -200 mV with specified loading.
@ .!!.ansi~ is measured ±200 mW from steady state voltage with specified loading.
<§) CS or WE must be high during addr-ess transitions.
69
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet UPD2147.PDF ] | |
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