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PDF UPD4104-1 Data sheet ( Hoja de datos )

Número de pieza UPD4104-1
Descripción 4096 x 1 STATIC NMOS RAM
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD4104-1 Hoja de datos, Descripción, Manual

NEe Microcomputers, Inc.
NEe
p.PD4104
p.PD41 04·1
pPD41 04·2
4096 x 1 STATIC NMOS RAM
DEseR IPTION
The J.LPD4104 is a high performance 4K static RAM. Organized as 4096 x 1, it uses
a combination of static storage cells with dynamic input/output circuitry to achieve
high speed and low power in the same device. Utilizing NMOS technology, the
J.LPD4104 is fully TTL compatible and operates with a single +5V ± 10% supply.
FEATURES ' . FastAccessTime-200ns (J.LPD4104-2)
• Very Low Stand-By Power - 28 mW Max.
• Low VCC Data Retention Mode to +3 Volts.
• Single +5V ±10% Supply.
• Fully TTL Compatible.
• Available in 18 Pin Plastic and Ceramic Dual-in-Line Packages.
• '3 Performance Ranges:
II
jlPD4104
jlPD4104-1
jlPD4104-2
ACCESS TIME
300 ns
250 ns
200 ns
RIWCYCLE
4S0 ns
.386 ~s
310 ns
SU PPL Y CURRENT
ACTIVE STANDBY LOWVCC
21 mA
5mA
5mA
21 mA
6mA
3.3mA
25mA
6mA
3.3mA
A3
A2
A1
AO
A"
AlO
DOUT
WE
VSS
VCC
A5
A4
A7
AS
Ag
AS
DIN
CE
PIN NAMES
AO-A11
CE
Address Inputs
Chip Enable
DIN
DOUT
VSS
VCC
WE
Data Input
Data Output
Ground
Power (+5V)
Write Enable
Rev/2
53

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UPD4104-1 pdf
ILPD4104
OPERATIONAL
DESCRIPTION
READCVCLE
The selection of one of the possible 4096 bits is made by virtue of the 12 address bits
presented at the inputs. These are latched into the chip by the negative going edge of
chip enable (CE). If the write enable (iNE) input is held at a high level (VIH) while the
CE input is clocked to a low level (VILl, a read operation will be performed. At the
access time (tAC), valid data will appear at the output. Since the output is unlatched
by a positive transition of CE, it will be in the high impedance state from the previous
cycle until the access time. It will go to the high impedance state again at the end of the
current cycle when CE goes high.
The address lines may be set up for the next cycle any time after the address hold time
has been satisfied for the current cycle.
WRITE CYCLE
Data to be written into a selected cell is latched into the chip by the later negative
transition of CE or WE. If WE is brought low before CE. the cycle is an "Early Write"
cycle, and data will be latched by CEo If CE is brought low before WE. as in a Read.
Modify·Write cycle, then data will be latched by WE.
II
If the cycle is an "Early Write" cycle, the output will remain in the high impedance
state. For a Read·Modify·Write cycle; the output will be active for the Modify and
Write portions of the memory cycle umil CE goes high. If WE is brought low after CE
but before the access time, the state of the output will be undefined. The desired data
will be written into the cell if data·in is valid on the leading edge of WE, tDI H is satisfied,
and WE occurs prior to CEgoing high by at least the minimum lead time (tWPL).
READ·MODIFV·WRITE
Read and Write cycles can be combined to allow reading of a selected location and then
modifying that data within the same memory cycle. Data is read at the access ti,me and
modified during a period defined by the user. New data is written between WE low and
the positive transition of CE. Data out will remain valid until the rising edge of CE. A
minimum R·M.-W cycle time can be calculated by tRMW = tAC +tMOD + twPL + tp +
3 tT; where tRMW is the cycle time, tAC is the access time, tMOD is the user defined
modify time, lWPL is the WE to CE lead time, tp is the CE hi9h time, and tT is one
transition time.
POWER DOWN MODE
In power down, data may be retained indefinitely by maintaining VCC at +3V.
However, prior to Vec going below VCC minimu!O (";4.5V) CE must be taken high
(VIH = 2.2V) and held for a minimum time period tpPD and maintained at VIH for
the entire standby period. After power is returned to VCC min or above, CE must be
held high for a minimum of tRC in order that the ,device may operate properly. See
power down waveforms herein. Any active cycle in progress prior to power down must
be completed so that tCE min is not violated.
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