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PDF CDP1822 Data sheet ( Hoja de datos )
| Número de pieza | CDP1822 | |
| Descripción | 256-Word by 4-Bit LSI Static Random-Access Memory | |
| Fabricantes | GE | |
| Logotipo |  |
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Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1822, CDP1822C
03
A2
AI
AD
A5
A6
A7
VSS
Dr I
001
012
22
2I
20
19
18
17
16
15
9 I.
10 13
" 12
TOP VIEW
Voo
O.
Riw
CSi
00
C52
DO.
014
003
DB
002
92CS-29976 RI
CDP1822, CDP1822C
TERMINAL ASSIGNMENTS
256-Word by 4-Bit LSI Static
Random-Access Memory
Features:
• Low operating current-8 mA at Voo=5 V
and cycle time=1 /is
• Industry standard pinout
• Two Chip-Select inputs-simple
memory expansion
• Memory retention for standby battery
voltage of 2 V min.
• Output-Disable for common I/O systems
• 3-state data output for bus-oriented
systems
• Separate data inputs and outputs
The RCA-CDP1822 and CDP1822C are 256-word by 4-blt
static random-access memories designed for use In memory
systems where high speed. low operating current. and
simplicity in use are desirable. The CDP1822 features high
speed and a wide operating voltage range. Both types have
separate data inputs and outputs and utilize single power
supplies of 4 to 6" volts for the CDP1822C and 4 to 10.5
volts for the CDP1822.
Two Chip-Select inputs are provided to simplify system
expansion. An Output Disable control provides Wire-OR
capability and is also useful in common Input/Output
systems. The Output Disable Input allows these RAMs to be
used in common data Input/Output systems by forcing the
output into a high-impedance state during a write operation
independent of the Chip-Select input condition. The output
assumes a high-impedance state when the Output Disable
is at high level or when the chip is deselected by CST and/or
CS2.
The high nOise immunity of the CMOS technology is
preserved in this design. For TTL interfacing at 5-V
operation. excellent system noise margin is preserved by
using an external pull-up resistor at each Input.
The CDP1822 and CDP1822C types are supplied in 22-lead
hermetic dual-in-line side-brazed ceramic packages (D
suffix). in 22-lead dual-in-line plastic packages (E suffix).
The CDP1822C is also available in chip form (H suffix).
OPERATIONAL MODES
MODE
Read
Write
Write
Standby
Standby
Output Disable
Chip Select 1
CS1
0
0
0
1
X
X
INPUTS
Chip Select 2 Output Disable
CS2 00
10
10
11
XX
0X
X1
Logic 1 =High Logic 0 =Low X =Don't Care
Read/Write
R/W
1
0
0
X
X
X
OUTPUT
Read
Data In
High Impedance
High Impedance
High Impedance
High Impedance
File Number 1074
654 _________________________________________________________
1 page  
Random-Access Memories (RAMs) _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1822, CDP1822C
DATA RETENTION CHARACTERiSTICS at TA = -40 to +85°C. see Fig. 3
CHARACTERISTIC
Min Data Retention
Voltage,
Data Retention Quiescent
Current,
Chip Deselect to Data
Retention Time,
Recovery to Normal
Operation Time,
VDDto VDR Rise and
Fall Time
VDR
IDD
tCDR
tRC
t"t,
TEST CONDITIONS
VDR
(V)
VDD
(V)
--
2-
-5
- 10
-5
- 10
25
'Typical values are for TA = 25° C and nominal VDD
LIMITS
CDP1822
CDP1822C
Min. Typ." Max. Min. Typ." Max.
- 1.5 2 - 1.5 2
UNITS
V
- 30 100 - 30 100 pA
600 -
- 600 -
-
300 - - - - -
600 - - 600 - - ns
300 - - - - -
1-
-
1 - - ps
92CS-30e05RJ
FIg. 3 - Low Voe data retentIOn tIming waveforms
!
I
WRITE
ADDRESS
DECODER
i
I
READ
ADDRESS
DECODER
92CS-27256R2
Fig. 4 - Memory cell configuration.
658 ______________________________________________________________
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CDP1822.PDF ] | |
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