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PDF UPD411-2 Data sheet ( Hoja de datos )

Número de pieza UPD411-2
Descripción FULLY DECODED RANDOM ACCESS MEMORY
Fabricantes NEC 
Logotipo NEC Logotipo



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No Preview Available ! UPD411-2 Hoja de datos, Descripción, Manual

NEe Microcomputers, Inc.
NEe
!J PD411
JJ PD411·1
f'PD411·2
,... PD411·3
flo PD411·4
oESCR I PTION
FEATUR ES
FULLY DECODED RANDOM ACCESS MEMORY
The J,lPD411 Family consists of six 4096 words by 1 bit dynamic N-channel MOS
RAMs. They are designed for memory applications where very low cost and large bit
storage are important design objectives. The J,lPD411 Family is designed using dynamic
circuitry which reduces the standby power dissipation.
Reading information from the memory is a non-destructive. Refreshing is easily
accomplished by performing one read cycle on each of the 64 row addresses. Each
row address must be refreshed every two milliseconds. The memory is refreshed
whether Chip Select is a logic high ol'a logic low.
All of these products are guaranteed for operation over the 0 to 70°C temperature
range.
Important features of the fJPD411 family are:
• Low Standby Power
• 4096 words x 1 bit Organization
• A single low-capacitance high level clock input with solid ±1 volt margins.
• Inactive Power/0.3 mW (Typ.)
• Power Supply: +12, +5, -5V
• Easy System Interface
• TTL Compatible (Except CE)
• Address Registers on the Chip
• Simple Memory Expansion by Chip Select
• Three State Output and TTL Compatible
• 22 pin Ceramic Dual-in-Line Package
• Replacement for INTEL'S 2107B, TI'S 4060 and Equivalent Devices.
• 5 Performance Ranges:
II
)1PD411
)1PD411·1
)1PD411·2
)1PD411·3
)1PD411-4
ACCESS TIME
300 ns
250 ns
200 ns
150 ns
135 ns
RIW CYCLE
470 ns
470 ns
400 ns
380 ns
320 ns
RMW CYCLE
650 ns
640 ns
520 ns
470 ns
320 ns
REFRESH TIME
? ms
2 ms
2 ms
2 ms
2 ms
PIN CONFIGURATION
VBB
Ag
AlO
A11
CS
DIN
2
4
5
6
jJPD
411
A2
VCC
8
9
10
11
vss
AS
A7
A6
VDD
CE
NC
As
A4
A3
WE
Rev/3
PIN NAMES
AO All
AO AS
CE
CS
DiN
DOUT
WE
VDD
VCC
VSS
VBB
NC
Address Inputs
Refresh Addresses
Chip Enable
Chip Select
Data Input
Data Output
Write Enable
Power (+12V)
Power (+5V)
Ground
IPower
No Connection
11

1 page




UPD411-2 pdf
TIMING WAVEFORMS
CE
READ CYCLE CD
'CE
","PD411
f - - - - - - tACC _ _ _ _ _~
CD For ,e/'esh cvcle 'Ow and column add,,,ss,,, musl be ,table TAC and ,ema,n
.table lor entn" tAH period
@ VOO 2V IS the reference level 1o, measurong tImIng of CE
@ VSS • 2V IS the ,,,ference level for mea"",ng !Omlng 01 CE
@ VIHMIN" Ihe ,,,ierence level 1of meawrong Hm,,,,,, 01 the addresses, CS,
WE and DIN
® VI LMAX IS the reference level 10' meaSU""9 tIming of Ihe add,e'S"5, Cs,
WE and DIN
® VSS .2.QV oS the reference lev"llor measurIng !lm,ng 01 Dour.
CD VSS -Q.BV I, the ,,,Ie,ence level lor mea!u,,,,,! limIng 01 Dour
II
WRITE CYCLE
t----------'Cy----------!
CE
V'H----~::::;;;:==.::::::.:===rt=;;;;;=::l r-++=o-:-----+-
----+-------,.j,,--'------f-'--""'-:-,..,.,,+- V,H
----+-------1.1"--------f-'--, '---"-=::.::...+-- VIL
Notes
G) VOO -2V IS Ihe ,,,Ierence level for mealu,;ng 1,m"1gof CE
® VSS '2v IS the ,eterence level for measu'""9 ItrT""9 01 CE
@ VIHMIN" The reference level lor measu"ngTlm,ng 01 The addresses, Cs,
WE and DIN
@) VILMAX" The releren<;e level 10' mea\U"ngT,mmg ollhe addresses, CS,
WE and DIN
CE
Ao - All
ANDCS
READ-MODI FY-WRITE CYCLE
t---------'RWC-----------i
tCRW 'CC
V'H
I~==~========~!:====~ct:::::==~_++_-------+_--VIH
---+-+r------------"\.,,---'------~-t_'_--.,,~r::___:_:_::_+-VIH
--+-+r-------------'1'----------I--::~p.-==:_+-V<L
DOUT =HIGH - -f-'-------------.J.----V.-L-'o---I-----i
- - -1-1-_-_IMPEOANCE L._-_-_-~-<A-CC-----------_----J--I1---------+--+===+---VOL
CDNote
WE mU$T be aT VIH un"l end (,)11CO
15

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