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PDF CDP1882C Data sheet ( Hoja de datos )

Número de pieza CDP1882C
Descripción CMOS 6-Bit Latch and Decoder Memory Interfaces
Fabricantes GE 
Logotipo GE Logotipo



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CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1881, CDP1881C,
CDP1882, CDP1882C
CLOCK
20 Voo
MA5
19 A8
MA'
18 A9
MA3
17 Ala
MA2
16 All
MAl
15 eso
MAO
MRO
MWR
vss
10
ffl
"" eS2
12 CS3
" CE
TOP VIEW
92CS- 3499BRI
CDP1881, CDP1881C
TERMINAL ASSIGNMENT
CMOS 6-Bit Latch and Decoder
Memory Interfaces
Features
Performs memory address latch and
decoder functions multiplexed or
non-multiplexed
Decodes up to 16 K-bytesofmemory
•• Interfaces dlfectly wIth CDP1800-
series microprocessors at
maximum clock frequency
Can replace existing CDP1866 and
CDP1867 (upward speed and
function capability)
CLOCK
MAS
MA'
MA'
MA2
MAl
MAO
IT
"ss
18 Voo
I.17 A8
A9
I.15 A 10
All
" eso
12 CST
CS2
10 m
TOP VIEW
92CS-34999
CDP1882,·CDP1882C
TERMINAL ASSIGNMENT
The RCA-CDP1881 and CDP1882 are CMOS 6-bit memory
latch and decoder circuits intended for use in CDP1800
series microprocessor systems. They can interface directly
with the multiplexed address bus of this system at maximum
clock frequency. and up to four 4K x 8-bit memories to
provide a 16K-byte memory system. With four 2K x 8-bit
memories an 8K-byte system can be decoded.
The devices are also compatible with non-multiplexed
address bus microprocessors. By connecting the clock
input to VDD, the latches are in the data-following mode and
the decoded outputs can be used in general-purpose
memory-system applications.
The COP1881 and CDP1882 are intended for use with 2K or
4K-byte RAMs and are identical except that in the CDP1882
MWJ'.! and MRO are excluded.
The CDP1881 and CDP1882 are functionally identical to the
CDP1881C and the CDP1882C. They differ in that the
COP1881 and COP1882 have a recommended operating
voltage range of 4 to 10 5 volts and their C versions have a
recommended operating voltage range of 4 to 6.5 volts.
The COP1881 and CDP1882 are supplied in 20-lead and
18-lead packages, respectively. The COP1881 is supplied
only in a dual-in-line plastic package (E suffix). The
COP1882 is supplied in dual-in-line, hermetic side-brazed
ceramic (0 suffix) and in plastic (E suffix) packages.
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY-VOLTAGE RANGE, (Voo)
(Voltage referenced to Vss terminal)
CDP1881 and CDP1882 ............................................................................................. -0.5 to +11 V
CDP1881C and CDPI882C ......................................................................... · ....... ·· ........ -0.5 to +7 V
INPUT VOL TAGE RANGE, ALL INPUTS .......................................................... ·· ...... ·.· ..... -05 to Voo +0.5 V
DC INPUT CURRENT. ANY ONE INPUT ................................................................................... ±10 mA
POWER DISSIPATION PER PACKAGE (Po)
ForTA: -40 to +60'C (PACKAGE TYPE E) .............................................................................. 500 mW
For Tf' : +60 to +85' C (PACKAGE TYPE E) ................................................. Derate Linearly at 12 mW/' C to 200 mW
For TA -55 to +loo'C (PACKAGE TYPE D) ............................................................................... 500 mW
For TA: +100 to 125'C (PACKAGE TYPE D) ............................................... Derate Linearly at 12 mW/'C to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
For TA: FULL PACKAGE-TEMPERATURE RANGE (All Package Types) ................................................... 100 mW
OPERATING-TEMPERATURE RANGE (TA):
PACKAGE TYPE D ............................................................................................... -55 to +125' C
PACKAGE TYPE E .................................................................................................-40 to +85'C
STORAGE-TEMPERATURE RANGE (Tstg) ........................................................................... -65 to +150'C
LEAD TEMPERATURE (DURING SOLDERING)
At distance 1116 ± 1/32 in. (1.59 ± 0.79 mm) from case for 10 s max ....................................................... +265'C
File Number 1367
468 _____________________________________________

1 page




CDP1882C pdf
CMOS Peripherals _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ __
CDP1881, CDP1881 C,
CDP1882, CDP1882C
SIGNAL DESCRIPTIONS/PIN FUNCTIONS
CLOCK: Latch-Input Control - a high at the clock input
will allow data to pass through the latch to the output pin.
Data is latched on the high to low transition of the clock
input. This input is connected to TPA in CDP1800-series
systems.
MAO-MA3: Address inputs to the high-byte address
latches.
MA4. MAS: I:!!ah-2address inputs decoded to produce
chip selects CSO - CS3.
MRD. MWR: MEMORY READ (Mi'i5i and MEMORY WRITE
(MWR) signal inputs on the CDP1881, CDP1881C A low at
either input, when the CE pin IS low, will enable the decoder
chip select outputs (CSO - CS3).
CE: CHIP ENABLE Input - a low at the CElnput of
CDP1882, CDP1882C will enable the chip select decoder A
low at the CElnput of CDP1881, CDP1881C, coinCident
with a low at either the MRD or MWR pin, will enable the
£!!!.E select decoder A high on this pin forces CSO, CS1,
CS2, and CS3 to a high (false) state.
A8-A11: Latched high-byte address outputs.
cso-CSi: One of four latched and decoded Chip Select
outputs.
VDD. Vss: Power and ground pinS, respectively.
APPLICATION INFORMATION
The CDP1881 and CDP1882 can interface directly with the
multiplexed address bus of the CDP1800-series
microprocessor family at maximum clock frequency. A
single CDP1881 or CDP1882 is capable of decoding up to
16K-bytes of memory.
The CDP1881 is provided with MRiS andMWR inputs for
controlling bus contention, and is especially useful for
interfacing with RAMs that do not have an output enable
function TO'Ei. Fig. 4 shows the CDP1881 in a minimum
system configuration which includes the CDP1833 ROM
(1 K x 8) and two 2K x 8 RAMS. The CDP1881, in this
example performs the following functions:
(1) Latch and decode high-order address bits for use as
chip selects.
(2) Gate chip selects with MRD and MWR to prevent bus
contention with the CPU
(3) Latch high-order address bits A8 to A11.
A system using the CDP1882 is shown in Fig. 5. The
CDP1882 performs the memory address latch and decoder
functions. Note that the RAM has an output enable (OE) pin
which eliminates the need for MR'b and MWR inputs on the
latch/decoder. Instead, the MRD line is connected directly
to the RAM output enable (aE) pin
In Fig. 6 the CDP1882 is used to decode a 16K-byte ROM
system conSisting of four CDM5332s.
WAiT
iii
TPA
CDPI800
SERI ES
CPU
TPA
CDPI833
IK .8
ROM
CLK
CDPI881
LATCHI
DECODER
All
CEO
IlIrn
MRD
iiWR -----
(2) 2K.8
RAMS
CS
R/W
DATA SUS
92CM-37294RI
* CEA • CE RAM No I
ns·n RAM No 2
FIg. 4 - Mmimum 1800-system usmg the CDP1881
472_________________________________________________________________

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