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PDF CDP1854AC Data sheet ( Hoja de datos )
| Número de pieza | CDP1854AC | |
| Descripción | Programmable Universal Asynchronous Receiver/Transmitter | |
| Fabricantes | GE | |
| Logotipo |  |
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Mode 1
Terminal Assignment
CMOS Peripherals
CDP1854A, CDP1854AC
Programmable Universal Asynchronous
Receiver/Transmitter (UART)
Features:
• Two operating modes:
• Baud rate-DC to 200 K bits/sec
Mode O-functionally compatible with
@ VDD=5 V
industry types such as the TR1602A
DC to 400 K bits/sec
Mode 1-interfaces directly with
@ VDD=10 V
CDP1800-series microprocessors • Fully programmable with externally se-
without additional components
lectable word length (5-8 bits), parity
• Full- or half-duplex operation
inhibit, even/odd parity, and 1, 1V" or
• Parity, framing, and overrun error
2 stop bits
detection
• False start bit detection
The RCA CDP1854A and CDP1854AC are silicon-gate
CMOS Universal Asynchronous Receiver/Transmitter
(UART) Circuits. They are designed to provide the necessary
formatting and control for interfacing between serial and
parallel data. For example, these UARTs can be used to
interface between a peripheral or terminal with serial I/O
ports and the 8-bit CDP1800-series microprocessor parallel
data bus system. The CDP1854A is capable of full duplex
operation, i.e., simultaneous conversion of serial input data
to parallel output data and parallel input data to serial
output data.
The CDP1854A UART can be programmed to operate in
one of two modes by using the mode control input. When
the mode input is high (MODE=1), the CDP1854A is
directly compatible with the CDP1800-series micro-
processor system without additional interface circuitry.
When the mode input is low (MODE=O), the device is
functionally compatible with industry standard UART's
such as the TR1602A. It is also pin compatible with these
types, except that pin 2 is used for the mode control input
instead of a VGG=-12 V supply connection.
The CDP1854A and the CDP1854AC are functionally
identical. The CDP1854A has a recommended operating-
voltage range of 4-10.5 volts, and the CDP1854AC has a
recommended operating-voltage range of 4-6.5 volts.
..
•
The CDP1854A and CDP1854AC are supplied in hermetic
40-lead dual-in-line ceramic packages (D suffix). in 40-lead
dual-in-line plastic packages (E suffix), and in 44-lead
plastic chip-carrier packages (0 suffix). The CDP1854AC is
also available in chip form (H suffix).
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4
40 T CLOCK
39 EPE
38 WLS I
37 WLS 2
R BUS 7
5
36 SBS
R BUS 6
R BUS 5
6
7
35 PI
34 CRL
R BUS 4
R BUS 3
33 T BUS 7
32 T BUS 6
R BUS 2
10
31 T BUS 5
R BUS 1
R BUS 0
II
12
30 T BUS 4
29 T BUS 3
PE 13
28 T BUS 2
FE 14
27 T BUS I
OE 15
26 T8US 0
SFo
16
25 SOO
RCLOCK
iiJilj
17
18
24 TSRE
23 THlf[
oA 19
22 THRE
SOl 20
21 MR
TOP VIEW
* PIN 2 NO CONNECTION
ON CDP6402
92CS-2B456RI
Mode 0
Terminal Assignment
TERMINAL ASSIGNMENT
R BUSS
Raus 5
R 8US 4
R BUS3
R 8US 2
NC
R 8US1
39
" 410
38
37
36
::---
NO-'~-0P VIEW
FILE
35
-::
F'I(CS31
CRLIRD/ViR}
T 8US 7
T8US6
T BUS 5
NC
T BUS4
M ~ T BUS3
15 31
"
17
18
19 20 21
30
29
22 23 24 25 26 27 28
T BUS 2
T BUS 1
TSUSO
gNOTE
MODE O(MODE 11 ~
~~
g ~ f I~
~ t:
44-Lead Plastic Chip-Carrier Package
(Q Suffix)
File Number1193
_______________________________________________________________ 387
1 page  
- - - - - - - - - - - - - - - - - - - - - - - - - - CMOS Peripherals
CDP1854A, CDP1854AC
Table I
SET' (INT =LOW)
CAUSE
DA
(Recei pt of data)
THRE*
(Ability to reload)
THRE·TSRE
(Transmitter done)
PSI
(Negative edge)
CTS
(Positive edge when THRE . TSRE)
Interrupt Set and Reset Conditions
RESET (INT =HIGH)
CONDITION
TIME
Read of data
TPB leading edge
Read of status or
write of character
Read of status or
write of character
Read of status
TPB leading edge
TPB leading edge
TPB trailing edge
Read of status
TPB leading edge
'Interrupts will occur only after the IE bit in the Control Register (see Table IV) has been set.
*THRE will cause an Interrupt only after the TR bit In the Control Register (see Table IV) has been set
Table II - Status Register BII Assignment
Bit 7 6 5 4 3 2 1 0
Signal
THRE TSRE PSI ES FE PE OE DA
Also Available at Terminal 22"
-
-
-
14 15 15 19'
'Polarity reversed at output terminal.
III
Bit Signal: Function
O-DATAAVAILABLE (DA):
When set high, this bit indicates that an entire character has
been received and transferred to the Receiver Holding
Register. This signal is also available at Term. 19 but with its
polarity reversed.
1-0VERRUN ERROR (OE):
When set high, this bit indicates that the Data Available bit
was not reset before the next character was transferred to
the Receiver Holding Register. This signal OR'ed with PE is
output at Term. 15.
2-PARITY ERROR (PE):
When set high, this bit indicates that the received parity bit
does not compare to that programmed by the EVEN
PARITY ENABLE (EPE) control. This bit is updated each
time a character is transferred to the Receiver Holding
Register. This signal OR'ed with OE is output at Term. 15.
3-FRAMING ERROR (FE):
When set high, this bit indicates that the received character
has no valid stop bit, i.e., 'the bit following the parity bit (if
programmed) is not a high-level voltage. This bit is updated
each time a character is transferred to the Receiver Holding
IReglster. This signal is also available at Term. 14.
I
4-EXTERNAL STATUS (ES):
__
This bit is set high by a low-level input at Term. 38 (ES).
5-PERIPHERAL STATUS INTERRUPT (PSI):
This bit is set high by a high-to-Iow voltage transition of
Term. 37 (f§.!). The INTERRUPT output (Term. 13) is also
asserted (INT=low) when this bit is set.
6-TRANSMITTER SHIFT REGISTER EMPTY (TSRE):
When set high, this bit indicates that the Transmitter Shift
Register has completed serial transmission of a full
character including stop bit(s). It remains set until the start
of transmission of the next character.
7-TRANSMITTER HOLDING REGISTER EMPTY (THRE):
When set high, this bit indicates that the Transmitter
Holding Register has transferred its contents to the
Transmitter Shift Register and may be reloaded with a new
character. Setting this bit also sets the THRE output (Term.
22) low and causes an INTERRUPT (INT=low), if TR is
high.
- - - - - - -_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 391
5 Page 
CMOS Peripherals
CDP1854A, CDP1854AC
:---t TT---j
TPB* ____________________________________~I
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~tDW-------l
_____________________________,
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*'-_______,Lt WD---*1,-______
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,I
RD/WR,CS2*~
* WRITE IS THE OVERLAP OF TPB, CSI, CS3= I AND CS2, RD/WR=o
Fig. 5 - Mode 1 CPU interface (WRITE) timing diagram.
92CM-31879
TPB ____________________________________~i" - - -tTT----""~j---------------------
RSEL -----------------------------..*~tRST----l :
----------------------~,
:!--tTRS-*: r--------------
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* READ IS THE OVERLAP OF CSI, CS3, RO/WR =I AND CS2 =0
92CM-318el
Fig. 6 - Mode 1 CPU interface (READ) timing diagram.
Mode Input Low (Mode = 0)
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T CLOCK
R CLOCK
1= VDO
2,3= VSS
21 =MR
III
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TRANSMITTER SECTION
ICAL SFD
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RECEIVER
BUS
RECEIVER SECTION
~
~
m
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Fig. 7 - Mode 0 block diagram (industry standard compatible).
397
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CDP1854AC.PDF ] | |
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