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PDF CDP6805E2C Data sheet ( Hoja de datos )

Número de pieza CDP6805E2C
Descripción CMOS 8-Bit Microprocessor
Fabricantes GE 
Logotipo GE Logotipo



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_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serle. Microprocessors and Microcomputers
CDP6805E2, CDP6805E2C
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TERMINAL ASSIGNMENT
CMOS 8-Bit Microprocessor
Hardware Fealures:
• Typical full speed operating power of
35mW@5V
• Typical WAIT mode power of 5 mW
• Typical STOP mode power of 25pW
• 112 bytes of on-chip RAM
• 16 bidirectional I/O lines
• InternalB-bit timer with software
programmable 7-bit presca/er
• External timer input
• Full external and timer interrupts
• Multiplexed address/data bus
• Master reset and power-on reset
• Capable of addressing up to BK bytes
of external memory
• Single 3- to 6-volt supply
• On-Chip oscillator
• 40-pin dua/-In-line package
• 44-/ead plastic chip-carrier package
The CDP6805E2 Microprocessor Unit (MPU) belongs to the
CDP6805 Family of CMOS Microcomputers. This 8-blt fully
static and expandable microprocessor contains a CPU, on-
chip RAM, I/O, and Timer. It is a low-power, low-cost
processor designed for mid-range applications in the
consumer, automotive, Industrial, and communications
markets where very low power consumption constitutes an
Importantiactor. The following are the major features ofthe
CDP6805E2 MPU.
Software Features:
• Efficient use of program spece
• Versatile interrupt handling
• True bit manipulation
• Addressing modes with Indexed addressing for tables
• Efficient instruction set
• Memory mapped I/O
• Two power saving standby modes
Po<'
A
110
L ". .
PAO
PA'
PA'
PA3
PM
PAS
PAS
PA7
Pori
9
1/0
L....
PBO
PBl
P.,
PB3
PB4
PBS
PBS
P97
p""
A
Oala
oor
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Pori Oala
B D"
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Accumulator
A
lode..
Reglsl8l'
Condilion
Cod.
5 RegIster C
SlaCk
6 Pomter Sp
rogram
Counter
High PCH
rogram
Counter
low peL
CPU
CPU
Conlrol
ALU
112)(8
RAM
Fig. 1 - Block diagram.
Mu,
Bu,
Dreve
Multtp"lted
Addressl
Oala
Bu.
Address
Orlve
AS
A' AddreS5
A'O Bu.
A"
A'2
Bu.
Control
AS Address Sirobe
OS Data 5uobe '.2)
5 R'W ReadIW"le
82CS-3I015
____________________________________________________________ 241

1 page




CDP6805E2C pdf
_________________ 6805-Series Microprocessors and Microcomputers
CDP6805E2, CDP6805E2C
IVLOW=O.8 V. VHIGH= VDD-2 V. VDD=5 ± 10%
Temp=O· to 70·C. CL on Port=50 pF. fOSC=5 MHzl
Address
Strobe
Port
Input
-
-
-
-
-
<
14-----tpVASL----~. . . .- - - t A S L P X
Port
Output
*The address strobe of the first cycle of the next Instruction as shown In Table 11
Fig. 3 - I/O port timing ivaveforms.
92CS-38017
Num
1
2
3
4
8
9
11
16
17
18
19
21
23
24
25
26
27
28
TABLE 2 - BUS TIMING (TA=TL to THo Vss=O VI See Figure 4
Characteristics
Cycle Time
Pulse Width. DS Low
Pulse Width. OS High or AD. WA. Low
Clock TranSlllon
A/W Hold
Non-Muxed Address Hold
A/W Delay from OS Fall
Non-Muxed Address Delay from AS A,se
MPU Aead Data Setup
Aead Data Hold
MPU Data Delay. Write
Write Data Hold
Muxed Address Delay from AS A,se
Muxed Address Valid to AS Fall
Muxed Address Hold
Delay OS Fall to AS Aise
Pulse Width. AS High
Delay. AS Fall to OS A,se
Symbol
tcyc
PWEL
PWEH
tr.t
tRW.
tAH
tAD
tADH
tDSA
tDHR
tDDW
tDHW
tBHD
tASL
tAHI
tASD
PWASH
tASED
fOSC=l MHz.
VOO=3 V
50 pF Load
Min Max
5000
2800
1800
-
10
800
-
DC
-
100
-
-
500
0 200
200 -
0 1000
-0
800 -
0 250
600 -
250 750
800 -
850 -
800 -
fOSC=5 MHz
VOD=5 V ± 10%.
1 TTL
and 130 pF Load
Min Max
1000
DC
560
375 -
- 30
10 -
100 -
- 300
0 100
115 -
0 160
- 120
55 -
0 120
55 -
60 180
160 -
175 -
160 -
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
_______________________________________________________________ 245

5 Page





CDP6805E2C arduino
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ 6805-Serles Microprocessors and Microcomputers
CDP6805E2, CDP6805E2C
Crystal - The CircUit shown in Figure 5 IS recom-
mended when uSing a crystal The Internal OSCillator IS
designed to Interface with an AT-cut parallel resonant
quartz crystal resonator In the frequency range
specified for 10SC In the electrical characteristics
table An external CMOS OSCillator IS recommended
when crystals outside the specified ranges are to be
used. The crystal and components should be mounted
as close as possible to the Input pins to minimize out-
put distortion and start-up stabilization time.
External Clock - An external clock should be ap-
plied to the OSCI input with the OSC2 Input not con-
nected, as shown In Figure 10
OSCI 39
OSC2 38
No
Connection
INCI
;;uP6805E2
Fig, 10 - External clock connection.
LI (Load Instruction) - This output IS uSfld to indicate that
a felch of the next opcode IS In progress. LI remainS low dur
Ing an External or Timer Interrupt Tile LI output IS only used
for certain debugging and test systems For norma! opera-
tions thiS pin IS not connected. The LI output IS capable of
driving one standard TTL load and 50 pF ThiS signal
overlaps Data Strobe
PAO-PA7 - These eight pins constitute Input/Output
Port A. Each line IS Individually programmed to be either an
Input or output unde, software control via ItS Data Direction
Register as shown below. An I/O pin IS programmed as an
output when the corresponding DDR bit IS set to a "1," and
as an Input when It IS set to a "0" In the output mode the
bits are latched and appear on the corresponding output
pins. An MPU read of the port bits programmed as outputs
retlect the last value written to that location. When program-
med as an Input, the Input data bltls) are not latched An
M PU read of the port bits programmed as Inputs reflects the
current status of the corresponding Input pins The
Read/Write port timing IS shown In Figure 3 See tYPical I/O
Port Circuitry In Figure 1,. DUring a Power-On Reset or ex-
ternal RESET all lines are configured as Inputs Izera In Data
Direction Register) The output port register IS not Initialized
by reset The TTL compatible three-state output buffers are
capable of driVing one standard TTL load and 50 pF The
DDR IS a read/write register
PBO-PB7 - These eight pins Interface to Input/Output
Port B Refer to PAO-PA7 description for details of opera-
tion
Data Direction
Register
Port A
Register
$0004
$0000
Pin PA7 PA6 PA5 PA4 PA3 PAl PAl PAO
Data Direction
Register
Port B
Register
$0005
$0001
Pin PB7 PB6 PB5 PB4 PB3 PB2 PB 1 PBO
92CS-38025
______________________________________________________________ 251

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