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PDF CD4724BMS Data sheet ( Hoja de datos )
| Número de pieza | CD4724BMS | |
| Descripción | CMOS 8-Bit Addressable Latch | |
| Fabricantes | Intersil Corporation | |
| Logotipo |  |
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CD4724BMS
December 1992
CMOS 8-Bit Addressable Latch
Features
Pinout
• High Voltage Type (20V Rating)
• Serial Data Input
• Active Parallel Output
• Storage Register Capability
• Master Clear
• Can Function as Demultiplexer
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
A0 1
A1 2
A2 3
Q0 4
Q1 5
Q2 6
Q3 7
VSS 8
CD4724BMS
TOP VIEW
16 VDD
15 RESET
14 WRITE DISABLE
13 DATA
12 Q7
11 Q6
10 Q5
9 Q4
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Multi-line Decoders
• A/D Converters
Description
CD4724BMS 8-bit addressable latch is a serial-input, parallel-
output storage register that can perform a variety of functions.
Data are inputted to a particular bit in the latch when that bit is
addressed (by means of inputs A0, A1, A2) and when WRITE
DISABLE is at a low level. When WRITE DISABLE is high, data
entry is inhibited; however, all 8 outputs can be continuously
read independent of WRITE DISABLE and address inputs.
Functional Diagram
WRITE DISABLE
DATA
1
A0
2
A1
3
A2
DECODER
RESET
VDD = 16
VSS = 8
14
13
8
4
Q0
5
Q1
6
Q2
7
Q3
9
Q4
10
Q5
11 Q6
12 Q7
A master RESET input is available, which resets all bits to a
logic “0” level when RESET and WRITE DISABLE are at a high
level. When RESET is at a high level, and WRITE DISABLE is
at a low level, the latch acts as a 1-of-8 demultiplexer; the bit
that is addressed has an active output which follows that data
input, while all unaddressed bits are held to a logic “0” level.
The CD4724BMS is supplied in these 16-lead outline pack-
ages:
Braze Seal DIP
Frit Seal DIP
Ceramic Flatpack
H4W
H1F
H6W
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
7-1267
File Number 3348
1 page  
Specifications CD4724BMS
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
LIMITS
PARAMETER
P Threshold Voltage
P Threshold Voltage
Delta
Functional
Propagation Delay Time
SYMBOL
CONDITIONS
VTP VSS = 0V, IDD = 10µA
∆VTP VSS = 0V, IDD = 10µA
F
TPHL
TPLH
VDD = 18V, VIN = VDD or GND
VDD = 3V, VIN = VDD or GND
VDD = 5V
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
NOTES
1, 4
1, 4
TEMPERATURE
+25oC
+25oC
MIN
0.2
-
1
1, 2, 3, 4
+25oC
+25oC
VOH >
VDD/2
-
3. See Table 2 for +25oC limit.
4. Read and Record
MAX
2.8
±1
VOL <
VDD/2
1.35 x
+25oC
Limit
UNITS
V
V
V
ns
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER
SYMBOL
DELTA LIMIT
Supply Current - MSI-2
Output Current (Sink)
Output Current (Source)
IDD
IOL5
IOH5A
± 1.0µA
± 20% x Pre-Test Reading
± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP
MIL-STD-883
METHOD
GROUP A SUBGROUPS
Initial Test (Pre Burn-In)
100% 5004
1, 7, 9
Interim Test 1 (Post Burn-In)
100% 5004
1, 7, 9
Interim Test 2 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Interim Test 3 (Post Burn-In)
100% 5004
1, 7, 9
PDA (Note 1)
100% 5004
1, 7, 9, Deltas
Final Test
100% 5004
2, 3, 8A, 8B, 10, 11
Group A
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B
Subgroup B-5
Sample 5005
1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas
Subgroup B-6
Sample 5005
1, 7, 9
Group D
Sample 5005
1, 2, 3, 8A, 8B, 9
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
READ AND RECORD
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
IDD, IOL5, IOH5A
Subgroups 1, 2, 3, 9, 10, 11
Subgroups 1, 2 3
CONFORMANCE GROUPS
Group E Subgroup 2
TABLE 7. TOTAL DOSE IRRADIATION
MIL-STD-883
METHOD
TEST
PRE-IRRAD
POST-IRRAD
5005
1, 7, 9
Table 4
READ AND RECORD
PRE-IRRAD
POST-IRRAD
1, 9 Table 4
FUNCTION
Static Burn-In 1
Note 1
OPEN
4 - 7, 9 - 12
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
OSCILLATOR
GROUND
VDD
9V ± -0.5V
50kHz
25kHz
1 - 3, 8, 13 - 15
16
7-1271
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet CD4724BMS.PDF ] | |
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